AD671

REV. B

–14–

AD671 TO ADSP-2100A INTERFACE

Figure 19 demonstrates the AD671 to ADSP-2100A interface.

The 2100A with a clock frequency of 12.5 MHz can execute an

instruction in one 80 ns cycle. The AD671 is configured to per-

form continuous time sampling. The DAV output of the AD671

is asserted at the end of each conversion. DAV can be used to

latch the conversion result into the two 574 octal D-latches. The

falling edge of the sampling clock is used to generate an inter-

rupt (IRQ3) for the processor. Upon interrupt, the ADSP-

2100A starts a data memory read by providing an address on

the DMA bus. The decoded address generates OE for the

latches and the processor reads their output over the DMA bus.

The conversion result is read within a single processor cycle.

AD671 TO ADSP-2101/ADSP-2102 INTERFACE

Figure 20 is identical to the 2100A interface except the sam-

pling clock is used to generate an interrupt (IRQ2) for the pro-

cessor. Upon interrupt the ADSP-2101A starts a data memory

read by providing an address on the Address (A) bus. The de-

code address generates OE for the D-latches and the processor

reads their output over the Data (D) bus. Reading the conver-

sion result is thus completed within a single processor cycle.

ADSP-2100A

DMA0:13

DMA0:15

DMACK

ADDRESS BUS

DECODE

+5V

Q0:7

D0:7

574

OE

Q0:7

D0:7

574

OE

DATA BUS

D0:3

DAV

BIT1:12

SAMPLING

CLOCK

ENCODE

16

8

4

8

8

4

DMRD

IRQ3

AD671

Figure 19. AD671 to ADSP-2100A Interface

ADSP-2101

A0:13

D0:15

ADDRESS BUS

DECODE

Q0:7

D0:7

574

OE

Q0:7

D0:7

574

OE

DATA BUS

D0:3

DAV

BIT1:12

SAMPLING

CLOCK

ENCODE

16

8

4

8

8

4

RD

IRQ2

AD671

Figure 20. AD671 to ADSP-2101/ADSP-2102 Interface

Figure 21. PCB Silkscreen and Component Placement

Diagram for Figures 5, 10 and 13