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AD677AD Datenblatt(PDF) 13 Page - Analog Devices |
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AD677AD Datenblatt(HTML) 13 Page - Analog Devices |
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13 / 16 page ![]() AD677 REV. A –13– The standard deviation of this distribution is approximately 0.5 LSBs. If less uncertainty is desired, averaging multiple con- versions will narrow this distribution by the inverse of the square root of the number of samples; i.e., the average of 4 conversions would have a standard deviation of 0.25 LSBs. DSP INTERFACE Figure 10 illustrates the use of the Analog Devices ADSP-2101 digital signal processor with the AD677. The ADSP-2101 FO (flag out) pin of Serial Port 1 (SPORT 1) is connected to the SAMPLE line and is used to control acquisition of data. The ADSP-2101 timer is used to provide precise timing of the FO pin. ADSP-2101 FO AD677 SAMPLE SERIAL PORT 0 CLK BUSY SCLK0 DR0 RFS0 DT0 TFS0 SDATA Figure 10. ADSP-2101 Interface The SCLK pin of the ADSP-2101 SPORT0 provides the CLK input for the AD677. The clock should be programmed to be approximately 2 MHz to comply with AD677 specifications. To minimize digital feedthrough, the clock should be disabled (by setting Bit 14 in SPORT0 control register to 0) during data ac- quisition. Since the clock floats when disabled, a pulldown resis- tor of 12 k Ω–15 kΩ should be connected to SCLK to ensure it will be LOW at the falling edge of SAMPLE. To maximize the conversion rate, the serial clock should be enabled immediately after SAMPLE is brought LOW (hold mode). The AD677 BUSY signal is connected to RF0 to notify SPORT0 when a new data word is coming. SPORT0 should be configured in normal, external, noninverting framing mode and can be programmed to generate an interrupt after the last data bit is received. To maximize the conversion rate, SAMPLE should be brought HIGH immediately after the last data bit is received. 102 9.5 86 82 2.5 90 94 98 8.5 4.5 3.5 V REF – Volts 106 5.5 6.5 7.5 THD S/(N+D) 10.0 Figure 11. S/(N+D) and THD vs. VREF, fS = 100 kHz (Calibra- tion is not guaranteed below +5 VREF) INPUT LEVEL – dB 105 10 0 40 20 –70 30 –80 70 50 60 80 90 100 –10 –20 –30 –40 –50 –60 THD S/(N+D) Figure 12. S/(N+D) and THD vs. Input Amplitude, fS = 100 kHz 0 –20 –40 –60 –80 –100 –120 –140 0 51015 20 25 30 35 40 45 50 FREQUENCY – kHz Figure 13. 4096 Point FFT at 100 kSPS, fIN = 1 kHz, VREF = 5 V 0 –20 –40 –60 –80 –100 –120 –140 0 5 10 15 20 25 30 35 40 45 48 FREQUENCY – kHz Figure 14. 4096 Point FFT at 100 kSPS, fIN = 1 kHz, VREF = 10 V |
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