AD7722

–7–

REV. 0

PIN FUNCTION DESCRIPTION

Mnemonic

Pin No.

Description

14

Clock logic power supply voltage for the analog modulator, +5 V

± 5%.

AGND1

10

Clock logic ground reference for the analog modulator.

20, 23

Analog Power Supply Voltage, +5 V

± 5%.

AGND

9, 13, 15,

Ground reference for analog circuitry.

19, 21, 25, 26

39

Digital Power Supply Voltage, +5 V

± 5%.

DGND

6, 28

Ground reference for digital circuitry.

REF1

22

Reference Input/Output. REF1 connects through 3 k

Ω to the output of the internal 2.5 V

reference and to the input of a buffer amplifier that drives the

Σ−∆ modulator. This pin can

also be overdriven with an external reference 2.5 V.

REF2

24

Reference Input/Output. REF2 connects to the output of an internal buffer amplifier used to

to drive the

Σ−∆ modulator. When REF2 is used as an input, REF1 must be connected

to AGND.

18

Positive terminal of the differential analog input.

16

Negative terminal of the differential analog input.

UNI

7

Analog input range select input. UNI selects the analog input range for either bipolar

or unipolar operation. A logic low input selects unipolar operation. A logic high input

selects bipolar operation.

CLKIN

11

Clock Input. Master clock signal for the device. The CLKIN pin interfaces the AD7722

internal oscillator circuit to an external crystal or to an external clock. A parallel resonant,

fundamental-frequency, microprocessor-grade crystal and a 1 M

Ω resistor should be

connected between the CLKIN and XTAL pin with two capacitors connected from each

pin to ground. Alternatively, the CLKIN pin can be driven with an external CMOS-

compatible clock. The AD7722 is specified with a clock input frequency of 12.5 MHz.

XTAL

12

Oscillator Output. The XTAL pin connects the internal oscillator output to an external

crystal. If an external clock is used, XTAL should be left unconnected.

P/S

8

Parallel/Serial interface select input. A logic high configures output data interface for parallel

mode operation. Serial mode operation is selected with the P/S set to a logic low.

CAL

27

Calibration Logic Input. A logic high input for a duration of one CLKIN cycle initiates a

calibration sequence for the device Gain and Offset Error.

RESET

17

Reset Logic Input. RESET is used to clear the offset and gain calibration registers. RESET is an

asynchronous input. RESET allows the user to set AD7722 to an uncalibrated state if the device

had been previously calibrated. A rising edge also resets the AD7722

Σ−∆ modulator by shorting

the integrator capacitors in the modulator. In addition RESET functions identically to the

SYNC pin described below.

CS

29

Chip select is a level sensitive logic input. CS enables the output data register for parallel mode

read operation. The CS logic level is sensed on the rising edge of CLKIN. The output data bus

is enabled when the rising edge of CLKIN senses a logic low level on CS if RD is also low. When

CS

is sensed high, the output data bits DB15–DB0 will be high impedance. In serial mode tie

CS

to a logic low.

SYNC

30

Synchronization Logic Input. SYNC is an asynchronous input. When using more than one

AD7722 operated from a common master clock, SYNC allows each ADC’s

Σ−∆ modulator

to simultaneously sample its analog input and update its output data register. A rising edge resets

the AD7722 digital filter sequencer counter to zero. After a SYNC, conversion data is not valid

until after the digital filter settles (reference Figure 7). DVAL goes low in the serial mode. When

the rising edge of CLKIN senses a logic low on SYNC (or RESET) the reset state is released; in

parallel mode, DRDY goes high. After the reset state is released, DVAL returns high after

8192 CLKIN cycles (128

× 64/f

convolution cycle of the digital filter (64 CLKIN periods), when valid data is ready to be read

from the output data register.