REV. C

–16–

AD7816/AD7817/AD7818

Read Operation

Figure 20 shows the timing diagram for a serial read from the

AD7817.

CS is brought low to enable the serial interface and RD/

WR is set logic high to indicate that the data transfer is a serial read

from the AD7817. The rising edge of RD/

WR clocks out the first

data bit (DB9), subsequent bits are clocked out on the falling edge

of SCLK (except for the first falling SCLK edge) and are valid on

the rising edge. 10 bits of data are transferred during a read opera-

tion. However, the user has the choice of clocking only eight bits if

the full 10 bits of the conversion result are not required. The serial

data can be accessed in a number of bytes if 10 bits of data are

being read. However, RD/

WR must remain high for the duration of

the data transfer operation. Before starting a new data read opera-

tion the RD/

WR signal must be brought low and high again. At the

state on the rising edge of the

CS or the falling edge of RD/WR,

whichever occurs first. The readback process is a destructive

process in that once the data is read back it is erased. A conversion

must be done again; otherwise no data will be read back.

Write Operation

Figure 20 also shows a control byte write operation to the AD7817.

The RD/

WR input goes low to indicate to the part that a serial

write is about to occur. The AD7817 control byte is loaded on

the rising edge of the first eight clock cycles of the serial clock

with data on all subsequent clock cycles being ignored. To carry

out a second successive write operation, the RD/

WR signal must

be brought high and low again.

Simplifying the Serial Interface

To minimize the number of interconnect lines to the AD7817,

the user can connect the

CS line to DGND. This is possible if

the AD7817 is not sharing the serial bus with another device. It

arrangement is compatible with the 8051 microcontroller. The

68HC11, 68HC05, and PIC16Cxx can be configured to operate

with a single serial data line. In this way the number of lines

required to operate the serial interface can be reduced to three,

i.e., RD/

WR, SCLK, and D

AD7816 AND AD7818 SERIAL INTERFACE MODE

The serial interface on the AD7816 and AD7818 is a 3-wire

interface with read and write capabilities. Data is read from the

DB9

DB8

DB7

DB0

DB1

DB7

DB6

DB5

DB1

DB0

SCLK

13

2

123

910

RD/

WR

CS

8

7

CONTROL BYTE

Figure 20. AD7817 Serial Interface Timing Diagram

output register and the control byte is written to the AD7816

mode and requires an externally applied serial clock to the SCLK

input to access data from the data register or write the control

byte. The RD/

WR line is used to determine whether data is

being written to or read from the AD7816 and AD7818. When

data is being written to the devices the RD/

WR line is set logic

low and when data is being read from the part the line is set

logic high (see Figure 21). The serial interface on the AD7816

and AD7818 are designed to allow the part to be interfaced to

systems that provide a serial clock that is synchronized to the

serial data, such as the 80C51, 87C51, 68HC11, 68HC05, and

PIC16Cxx microcontrollers.

Read Operation

Figure 21 shows the timing diagram for a serial read from the

AD7816 and AD7818. The RD/

WR is set logic high to indicate

that the data transfer is a serial read from the devices. When

RD/

WR is logic high the D

and the first data bit (DB9) appears on the pin. Subsequent bits

are clocked out on the falling edge of SCLK, starting with the

second SCLK falling edge after RD/

WR goes high and are valid

on the rising edge of SCLK. Ten bits of data are transferred

during a read operation. However the user has the choice of

clocking only eight bits if the full 10 bits of the conversion result

are not required. The serial data can be accessed in a number of

bytes if 10 bits of data are being read; however, RD/

WR must

remain high for the duration of the data transfer operation. To

carry out a successive read operation the RD/

WR pin must be

brought logic low and high again. At the end of the read opera-

of RD/

WR.

Write Operation

A control byte write operation to the AD7816 and AD7818 is

also shown in Figure 21. The RD/

WR input goes low to indicate

to the part that a serial write is about to occur. The AD7816

and AD7818 control bytes are loaded on the rising edge of the

first eight clock cycles of the serial clock with data on all subse-

quent clock cycles being ignored. To carry out a successive write

to the AD7816 or AD7818 the RD/

WR pin must be brought

logic high and low again.