REV. 0

AD8381

–13–

AD8381

AD8381

DB(0:9)

CLK

XFR

STSQ

INV

CH 0

CH 2

CH 4

CH 6

CH 8

CH 10

CH 1

CH 3

CH 5

CH 7

CH 9

CH 11

12–CHANNEL

LCD

VID0

VID1

VID2

VID3

VID4

VID5

VREFHI

VMID

VREFLO

DB(0:9)

CLK

XFR

STSQ

INV

VREFHI

VMID

VREFLO

VID0

VID2

VID3

VID4

VID5

E/O

E/O

R/L

R/L

VID1

REFERENCES

VREFHI

VCOM

IMAGE PROCESSOR

DB(0:9)

CLK

XFR

STSQ1

STSQ2

INV1

INV2

E/O1

E/O2

R/L

H. REVERSE

CLK

CLK

CLK

CLK

STSQ1

STSQ2

INV1

INV2

HSTART

6 COUNTER

+2

PIXEL CLK

HSYNC

VSYNC

6 COUNTER

Figure 9. Single Data Bus 12-Channel Even/Odd System Block Diagram

CH 0

CH 2

CH 4

CH 6

CH 8

CH 10

CH 1

CH 3

CH 5

CH 7

CH 9

CH 11

12–CHANNEL

LCD

AD8381

AD8381

DB(0:9)

CLK

XFR

STSQ

INV

VID0

VID1

VID2

VID3

VID4

VID5

VREFHI

VMID

VREFLO

DB(0:9)

CLK

XFR

STSQ

INV

VREFHI

VMID

VREFLO

VID0

VID1

VID2

VID3

VID4

VID5

E/O

E/O

R/L

R/L

REFERENCES

VREFHI

VCOM

IMAGE PROCESSOR

DB1(0:9)

CLK

XFR

STSQ

INV1

INV2

E/O

R/L

H. REVERSE

CLK

HSYNC

VSYNC

INV1

INV2

DB2(0:9)

D(0:9) ODD

“1”

HSTART

D(0:9) EVEN

6 COUNTER

PIXEL CLK

+2

D(0:9) EVEN

D(0:9) ODD

Figure 10. Dual Parallel Data Bus 12-Channel System Block Diagram