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EM47DM0888SBA Datenblatt(PDF) 21 Page - Eorex Corporation

Teilenummer EM47DM0888SBA
Bauteilbeschribung  JEDEC Standard VDD/VDDQ
PDF  39 Pages
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Hersteller  EOREX [Eorex Corporation]
Direct Link  http://www.eorex.com
Logo EOREX - Eorex Corporation

EM47DM0888SBA Datenblatt(HTML) 21 Page - Eorex Corporation

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EM47DM0888SBA
May. 2011
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AC Operating Test Characteristics
(VDD, VDDQ=1.5V±0.075V)
Speed Bin
-150
(DDR3-1333)
-187
(DDR3-1066)
CL-nRCD-nRP
9-9-9
7-7-7
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
Notes
tWLS
Write leveling setup time from
rising CK,/CK crossing to rising
DQS,/DQS crossing
165
-
195
-
ps
tWLH
Write leveling hold time from
rising DQS,/DQS crossing to
rising CK,/CK crossing
165
-
195
-
ps
tWLO
Write leveling output delay
0
7.5
0
9
ns
tWLOE
Write leveling output error
0
2
0
2
ns
tCK (abs)
Absolute clock period
tCK (avg)min+
tJIT(per)min
tCK (avg)max+
tJIT (per)max
tCK (avg)min+
tJIT (per)min
tCK (avg)max+
tJIT (per)max
ps
tCH (abs)
Absolute clock high pulse width
0.43
-
0.43
-
tCK
(avg)
30
tCL (abs)
Absolute clock low pulse width
0.43
-
0.43
-
tCK
(avg)
31
tJIT (per)
Clock period jitter
-70
70
-80
80
ps
tJIT (per,lck)
Clock period jitter during DLL
locking period
-60
60
-70
70
ps
tJIT (cc)
Cycle to cycle period jitter
-
140
-
160
ps
tJIT (cc,lck)
Cycle to cycle period jitter during
DLL locking period
-
120
-
140
ps
tERR (2per)
Cumulative error across 2 cycles
-103
103
-118
118
ps
tERR (3per)
Cumulative error across 3 cycles
-122
122
-140
140
ps
tERR (4per)
Cumulative error across 4 cycles
-136
136
-155
155
ps
tERR (5per)
Cumulative error across 5 cycles
-147
147
-168
168
ps
tERR (6per)
Cumulative error across 6 cycles
-155
155
-177
177
ps
tERR (7per)
Cumulative error across 7 cycles
-163
163
-186
186
ps
tERR (8per)
Cumulative error across 8 cycles
-169
169
-193
193
ps
tERR (9per)
Cumulative error across 9 cycles
-175
175
-200
200
ps
tERR (10per)
Cumulative error across 10
cycles
-180
180
-205
205
ps
tERR (11per)
Cumulative error across 11
cycles
-184
184
-210
210
ps
tERR (12per)
Cumulative error across 12
cycles
-188
188
-215
215
ps
tERR (nper)
Cumulative error across
n= 13,14,… 49,50 cycles
tERR (nper)min=(1+0.68ln(n))*tJIT (per)min
tERR (nper)max=(1+0.68ln(n))*tJIT (per)max
ps
32



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