AD9054ASLASHPCB datasheet(14/19 Pages) AD

14 / 19 page

AD9054A

–14–

REV. B

Applications that call for the AD9054A to be synchronized at

power-up or only periodically during calibration/reset (i.e., valid

data is not required prior to synchronization), need only be

concerned with the timing of the falling edge of DS. The falling

edge of DS must satisfy the setup time defined by Figure 2 and

the specification table. In this case the DS hold time specifica-

tion on the rising edge can be ignored.

Applications that will continuously update the synchronization

command need to treat the DS signal as a pulse and satisfy

timing requirements on both rising and falling edges. It is easiest

to consider the DS signal in this case to be a pulse train at one

half the encode rate, the positive pulse nominally bracketing the

ENCODE falling edge on alternate cycles as shown in the tim-

ing diagram (Figure 2b). Both the falling and rising edges of DS

must satisfy minimum setup (tSDS) and hold (tHDS) times with

respect to the falling edges of ENCODE. This timing require-

ment produces a tight timing window at higher encode rates.

Synchronization by a single reset edge results in a simpler timing

solution in many applications. For example, synchronization

may be provided at the beginning of each graphics line or frame.

The data are presented at the output of the AD9054A in a ping-

pong (alternating) fashion to optimize the performance of the

converter. It may be aligned for presentation as sixteen bits in

parallel by adding a register stage to the output.

In Dual Channel Mode, the converted data is produced five

clock cycles after the rising edge of ENCODE on which the

sample is taken (five pipeline delays).

In Figure 36, the converter is operating in Dual Port Mode,

with data coming alternately out of Port A and Port B. The

figure illustrates how the output data may be aligned with an

output latch to produce a 16-bit output at 1/2 the conversion

clock rate. The Data Sync input must be properly exercised to

time the A Port with the synchronizing latch.

VIN

0.1 F

CLOCK

VREF OUT

VREF IN

AIN

DEMUX

AD9054A

DS ENC ENC

A PORT

'573

B PORT

'74

DIVIDE

BY 2

NC = NO CONNECT

Figure 36. Dual Port Mode—Aligned Output Data

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