AD9775EB datasheet(22/48 Pages) AD

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REV. 0

AD9775

–22–

fDATA – MHz

050

72.0

100

150

200

72.5

(MOD. ON)

73.0

73.5

74.0

74.5

75.0

75.5

76.0

Figure 16. IAVDD vs. fDATA vs. Interpolation Rate,

PLL Disabled

fDATA – MHz

050

100

150

200

Figure 17. ICLKVDD vs. fDATA vs. Interpolation Rate,

PLL Disabled

SLEEP/POWER-DOWN MODES

(Control Register 00h, Bits 3 and 4)

The AD9775 provides two methods for programmable reduction

in power savings. The sleep mode, when activated, turns off the

DAC output currents but the rest of the chip remains functioning.

When coming out of sleep mode, the AD9775 will immediately

return to full operation. Power-down mode, on the other hand,

turns off all analog and digital circuitry in the AD9775 except

for the SPI port. When returning from power-down mode, enough

clock cycles must be allowed to flush the digital filters of random

data acquired during the power-down cycle.

ONE/TWO PORT INPUT MODES

The digital data input ports can be configured as two independent

ports or as a single (one port mode) port. In two port mode, the

AD9775 can be programmed to generate an externally avail-

able data rate clock (DATACLK) for the purpose of data

synchronization. Data at the two input ports can be latched into

the AD9775 on every rising clock edge of DATACLK. In one

port mode, P2B12 and P2B13 from input data Port 2 are

redefined as IQSEL and ONEPORTCLK, respectively. The

input data in one port mode is steered to one of the two internal

data channels based on the logic level of IQSEL. A clock signal,

ONEPORTCLK, is generated by the AD9775 in this mode for

the purpose of external data synchronization. ONEPORTCLK

runs at the input interleaved data rate which is 2

× the data rate

at the internal input to either channel.

Test configurations showing the various clocks that are required and

produced by the AD9775 in the PLL and one/two port modes

are given in Figures 55 through 58. Jumper positions needed to

operate the AD9775 evaluation board in these modes are given

as well.

PLL ENABLED, TWO PORT MODE

(Control Register 02h, Bits 6–0 and 04h, Bits 7–1)

With the phase-locked loop (PLL) enabled and the AD9775 in

two port mode, the speed of CLKIN is inherently that of the input

data rate. In two port mode, Pin 8 (DATACLK/PLL_ LOCK)

can be programmed (Control Register 01h, Bit 0) to function as

either a lock indicator for the internal PLL or as a clock running

at the input data rate. When Pin 8 is used as a clock output

(DATACLK), its frequency is equal to that of CLKIN. Data at

the input ports is latched into the AD9775 on the rising edge of the

CLKIN. Figure 18 shows the delay, tOD, inherent between the

rising edge of CLKIN and the rising edge of DATACLK, as well

as the setup and hold requirements for the data at Ports 1 and 2.

Note that the setup and hold times given in Figure 18 are the

input data transitions with respect to CLKIN. tOD can vary with

CLKIN speed, PLL divider setting, and interpolation rate. It is

therefore highly recommended that the input data be synchro-

nized to CLKIN rather than DATACLK when the PLL is enabled.

Note that in two port mode (PLL enabled or disabled), the data

rate at the interpolation filter inputs is the same as the input data

rate at Ports 1 and 2.

The DAC output sample rate in two port mode is equal to the

clock input rate multiplied by the interpolation rate. If zero

stuffing is used, another factor of two must be included to calcu-

late the DAC sample rate.

DATACLK Inversion

(Control Register 02h, Bit 4)

By programming this bit, the DATACLK signal shown in

Figure 18 can be inverted. With inversion enabled, tOD will

refer to the time between the rising edge of CLKIN and the

falling edge of DATACLK. No other effect on timing will occur.

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