AD9883SLASHPCB datasheet(20/24 Pages) AD

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AD9883

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2-WIRE SERIAL CONTROL PORT

A 2-wire serial interface control interface is provided. Up to four

AD9883 devices may be connected to the 2-wire serial interface,

with each device having a unique address.

The 2-wire serial interface comprises a clock (SCL) and a bidi-

rectional data (SDA) pin. The Analog Flat Panel Interface acts

as a slave for receiving and transmitting data over the serial inter-

face. When the serial interface is not active, the logic levels on

SCL and SDA are pulled HIGH by external pull-up resistors.

Data received or transmitted on the SDA line must be stable for

the duration of the positive-going SCL pulse. Data on SDA must

change only when SCL is LOW. If SDA changes state while SCL

is HIGH, the serial interface interprets that action as a start or

stop sequence.

There are six components to serial bus operation:

• Start Signal

• Slave Address Byte

• Base Register Address Byte

• Data Byte to Read or Write

• Stop Signal

When the serial interface is inactive (SCL and SDA are HIGH)

communications are initiated by sending a start signal. The start

signal is a HIGH-to-LOW transition on SDA while SCL is

HIGH. This signal alerts all slaved devices that a data transfer

sequence is coming.

The first eight bits of data transferred after a start signal com-

prising a 7-bit slave address (the first seven bits) and a single R/

bit (the eighth bit). The R/

W bit indicates the direction of data

transfer, read from (1) or write to (0) the slave device. If the

transmitted slave address matches the address of the device (set by

the state of the SA1-0 input pins in Table XXXIV, the AD9883

acknowledges by bringing SDA LOW on the 9th SCL pulse. If

the addresses do not match, the AD9883 does not acknowledge.

Table XXXIV. Serial Port Addresses

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(MSB)

01100

01101

Data Transfer via Serial Interface

For each byte of data read or written, the MSB is the first bit of

the sequence.

If the AD9883 does not acknowledge the master device during a

write sequence, the SDA remains HIGH so the master can

generate a stop signal. If the master device does not acknowledge

the AD9883 during a read sequence, the AD9883 interprets this

as “end of data.” The SDA remains HIGH so the master can

generate a stop signal.

Writing data to specific control registers of the AD9883 requires

that the 8-bit address of the control register of interest be written

after the slave address has been established. This control register

address is the base address for subsequent write operations. The

base address autoincrements by one for each byte of data written

after the data byte intended for the base address. If more bytes

are transferred than there are available addresses, the address will

not increment and remain at its maximum value of 14h. Any base

address higher than 14h will not produce an acknowledge signal.

Data is read from the control registers of the AD9883 in a similar

manner. Reading requires two data transfer operations:

The base address must be written with the R/

W bit of the slave

address byte LOW to set up a sequential read operation.

Reading (the R/

W bit of the slave address byte HIGH) begins at

the previously established base address. The address of the read

To terminate a read/write sequence to the AD9883, a stop sig-

nal must be sent. A stop signal comprises a LOW-to-HIGH

transition of SDA while SCL is HIGH.

A repeated start signal occurs when the master device driving

the serial interface generates a start signal without first generat-

ing a stop signal to terminate the current communication. This

is used to change the mode of communication (read, write)

between the slave and master without releasing the serial inter-

face lines.

SDA

SCL

tBUFF

tSTAH

tDHO

tDSU

tDAL

tDAH

tSTASU

tSTOSU

Figure 9. Serial Port Read/Write Timing

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