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NCP4304 Datenblatt(PDF) 5 Page - ON Semiconductor

Teilenummer NCP4304
Bauteilbeschribung  Secondary Side Synchronous Rectification Driver for High Efficiency SMPS Topologies
PDF  32 Pages
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Hersteller  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
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NCP4304 Datenblatt(HTML) 5 Page - ON Semiconductor

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NCP4304A, NCP4304B
http://onsemi.com
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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC
= 12 V, Cload = 0 nF, R_min_ton = R_min_toff = 10 kW, Vtrig = 0 V, f_CS = 100 kHz, DC_CS = 50%, VCS_high = 4 V, VCS_low = −1 V unless
otherwise noted)
Symbol
Unit
Max
Typ
Min
Pin
Rating
DRIVE OUTPUT
tr_A
Output voltage rise−time for A version (Cload = 10 nF)
8
120
ns
tr_B
Output voltage rise−time for B version (Cload = 10 nF)
8
80
ns
tf_A
Output voltage fall−time for A version (Cload = 10 nF)
8
50
ns
tf_B
Output voltage fall−time for B version (Cload = 10 nF)
8
35
ns
Roh
Driver source resistance (Note 3)
8
1.8
7
W
Rol
Driver sink resistance
8
1
2
W
IDRV_pk(source) Output source peak current
8
2.5
A
IDRV_pk(sink)
Output sink peak current
8
5
A
VDRV(min_A)
Minimum drive output voltage for A version (VCC = VCCoff + 200 mV)
8
8.3
V
VDRV(min_B)
Minimum drive output voltage for B version (VCC = VCCoff + 200 mV)
8
4.5
V
VDRV(CLMP_A) Driver clamp voltage for A version (12 < VCC < 28, Cload = 1 nF)
8
10
12
14.3
V
VDRV(CLMP_B) Driver clamp voltage for B version (12 < VCC < 28, Cload = 1 nF)
8
5
6
8
V
CS INPUT
Tpd_on
The total propagation delay from CS input to DRV output turn on
(Vcs goes down from 4 V to −1 V, tf_CS = 5 ns, COMP pin connected
to GND)
5, 8
60
90
ns
Tpd_off
The total propagation delay from CS input to DRV output turn off
(Vcs goes up from −1 V to 4 V, tr_CS = 5 ns, COMP pin connected to
GND), (Note 3)
5, 8
40
55
ns
Ishift_CS
Current sense input current source (VCS = 0 V)
5
95
100
105
mA
Vth_cs_on
Current sense pin turn−on input threshold voltage
5, 8
−120
−85
−50
mV
Vth_cs_off
Current sense pin turn−off threshold voltage, COMP pin connected
to GND (Note 3)
5, 8
−1
0
mV
Gcomp
Compensation inverter gain
5,6,8
−1
ICS_Leakage
Current Sense input leakage current, VCS = 200 Vdc
5
1
mA
TRIGGER/DISABLE INPUT
ttrig_pw_min
Minimum trigger pulse width (Note 3)
4
30
ns
Vtrig
Trigger input threshold voltage (Vtrig goes up)
4
1.5
2.5
V
tp_trig
Propagation delay from trigger input to the DRV output (Vtrig goes up
from 0 to 5 V, tr_trig = 5 ns)
4
13
30
ns
ttrig_light_load
Light load turn off filter duration
4
70
100
130
ms
ttrig_light_load_rec. IC operation recovery time when leaving light load disable mode
(Vtrig goes down from 5 to 0 V, tf_trig = 5 ns)
4
10
us
tt_blank
Blanking time of trigger/dis during DRV rising edge (VCS < Vth_cs_on,
single pulse on trigger/dis ttrig_pw = 50 ns)
4
120
ns
Itrig
Trigger input pull down current (Vtrig = 5 V)
4
10
mA
MINIMUM Ton AND Toff ADJUST
Ton_min
Minimum Ton period (RT_on_min = 0 W)
3
130
ns
Toff_min
Minimum Toff period (RT_off_min = 0 W)
2
560
600
690
ns
Ton_min
Minimum Ton period (RT_on_min = 10 kW)
3
0.9
1.0
1.1
ms
Toff_min
Minimum Toff period (RT_off_min = 10 kW)
2
0.9
1.0
1.1
ms
Ton_min
Minimum Ton period (RT_on_min = 50 kW)
3
4.8
ms
Toff_min
Minimum Toff period (RT_off_min = 50 kW)
2
4.8
ms
3. Guaranteed by design.



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