ADP1111

–12–

REV. 0

This occurs in the step-up mode when the following condition is

met:

<

1

1

− DC

where DC is the ADP1111’s duty cycle. When this relationship

exists, the inductor current does not go all the way to zero

during the time that the switch is OFF. When the switch turns

on for the next cycle, the inductor current begins to ramp up

from the residual level. If the switch ON time remains constant,

the inductor current will increase to a high level (see Figure 24).

This increases output ripple and can require a larger inductor

resistor, output ripple current can be maintained at the design

Figure 24.

Figure 25.

Q1 is the ADP1111’s internal power switch that is paralleled by

sense transistor Q2. The relative sizes of Q1 and Q2 are scaled

internal 80

Ω resistor and through the R

resistors parallel the base-emitter junction of the oscillator-

exceeds 0.6 V, Q3 turns on and terminates the output pulse. If

only the 80

Ω internal resistor is used (i.e. the I

72kHz

OSC

POWER

SWITCH

SW2

SW1

DRIVER

80

Ω

(INTERNAL)

200

(EXTERNAL)

Q2

ADP1111

Q1

Q3

R1

Figure 26. ADP1111 Current Limit Operation

The delay through the current limiting circuit is approximately

1

µs. If the switch ON time is reduced to less than 3 µs, accuracy

of the current trip-point is reduced. Attempting to program a

switch ON time of 1

µs or less will produce spurious responses

in the switch ON time; however, the ADP1111 will still provide

a properly regulated output voltage.

PROGRAMMING THE GAIN BLOCK

The gain block of the ADP1111 can be used as a low-battery

detector, error amplifier or linear post regulator. The gain block

consists of an op amp with PNP inputs and an open-collector

NPN output. The inverting input is internally connected to the

ADP1111’s 1.25 V reference, while the noninverting input is

available at the SET pin. The NPN output transistor will sink

about 300

µA.

Figure 27a shows the gain block configured as a low-battery

monitor. Resistors R1 and R2 should be set to high values to

reduce quiescent current, but not so high that bias current in

the SET input causes large errors. A value of 33 k

Ω for R2 is a

good compromise. The value for R1 is then calculated from the

formula:

R1

=

1.25 V

R2

gain block output is an open-collector NPN, a pull-up resistor

should be connected to the positive logic power supply.

ADP1111

1.25V

REF

GND

AO

5V

47k

TO

PROCESSOR

R1

R2

SET

33k

R1= –––––––––

35.1µA

Figure 27a. Setting the Low Battery Detector Trip Point

200mA/div

200mA/div