ADP3415LRMZ-REEL datasheet(2/12 Pages) AD

2 / 12 page

REV. B

–2–

ADP3415–SPECIFICATIONS1

(TA = 0 C to 100 C, VCC = 5 V, VBST – VSW = 5 V, SD = 5 V, CDRVH = CDRVL = 3 nF,

unless otherwise noted.)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

SUPPLY (VCC)

Quiescent Current

ICCQ

Shutdown Mode

VSD = 0.8 V

µA

Operating Mode

VSD = 5 V, No Switching

1.2

UNDERVOLTAGE LOCKOUT

(UVLO)

UVLO Threshold

VCCUVLO

3.9

4.15

4.5

UVLO Hysteresis

VCCHUVLO

0.05

LOW-SIDE DRIVER SHUTDOWN

(

DRVLSD)

Input Voltage High

VIH

2.0

Input Voltage Low3

VIL

0.8

Propagation Delay

3, 4

tpdlDRVLSD

(See Figure 3)

tpdhDRVLSD

SHUTDOWN (

SD)

Input Voltage High

VIH

2.0

Input Voltage Low3

VIL

0.8

INPUT (IN)

Input Voltage High

VIH

2.0

Input Voltage Low

VIL

0.8

THERMAL SHUTDOWN (THSD)

THSD Threshold

TSD

TJ = TA

165

°C

THSD Hysteresis

THSD

TJ = TA

°C

HIGH-SIDE DRIVER (DRVH)

Output Resistance, DRVH–BST

1.5

3.5

Ω

Output Resistance, DRVH–SW

0.85

2.0

Ω

DRVH Transition Times

trDRVH

VBST – VSW = 4.6 V

(See Figure 4)

tfDRVH

DRVH Propagation Delay

4, 5

tpdhDRVH

VBST – VSW = 4.6 V, VDLY = 0 V

RDLY

≥ 120 kΩ

100

200

(See Figure 4)

tpdlDRVH

LOW-SIDE DRIVER (DRVL)

Output Resistance, DRVL–VCC

1.6

3.0

Ω

Output Resistance, DRVL–GND

1.0

3.0

Ω

DRVL Transition Times

trDRVL

VBST – VSW = 4.6 V

(See Figure 4)

tfDRVL

VBST – VSW = 4.6 V

DRVL Propagation Delay

4, 5, 6

tpdhDRVL

VBST – VSW = 4.6 V

(See Figure 4)

tpdlDRVL

VBST – VSW = 4.6 V

SW Transition Timeout

tSWTO

VBST – VSW = 4.6 V

130

300

Zero-Crossing Threshold

VZC

1.6

NOTES

1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2Including I

BSTQ quiescent current.

3The signal source driving the pin must have 70

µA (typ) pull-down strength to make a high-to-low transient, and 20 µA (typ) pull-up strength to make a low-to-high

transient. The pin does not represent load (<100 nA) in static low (<0.8 V) and static high (>2.0 V) logic states (see TPC 3.) The pin can be driven with standard

TTL logic level source.

4Guaranteed by characterization.

5For propagation delays, tpdh refers to the specified signal going high, tpdl refers to it going low.

6Propagation delay measured until DRVL begins its transition.

7The turn-on of DRVL is initiated after IN goes low by either V

SW crossing a ~1.6 V threshold or by expiration of t SWTO.

Specifications subject to change without notice.

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