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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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OP495GS Datenblatt(PDF) 3 Page - Analog Devices |
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OP495GS Datenblatt(HTML) 3 Page - Analog Devices |
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3 / 12 page  ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions Min Typ Max Units INPUT CHARACTERISTICS Offset Voltage VOS 30 300 µV –40 °C ≤ T A ≤ +125°C 800 µV Input Bias Current IB VCM = 0 V 7 20 nA VCM = 0 V, –40°C ≤ TA ≤ +125°C30 nA Input Offset Current IOS VCM = 0 V ±1 ±3nA VCM = 0 V, –40°C ≤ TA ≤ +125°C ±5nA Input Voltage Range VCM –15 +13.5 V Common-Mode Rejection Ratio CMRR –15.0 V ≤ V CM ≤ +13.5 V, –40°C ≤ TA ≤ +125°C 90 110 dB Large Signal Voltage Gain AVO RL = 10 kΩ 1000 4000 V/mV Offset Voltage Drift ∆V OS/∆T 1 µV/°C OUTPUT CHARACTERISTICS Output Voltage Swing High VOH RL = 100 kΩ to GND 14.95 V RL = 10 kΩ to GND 14.80 V Output Voltage Swing Low VOL RL = 100 kΩ to GND –14.95 V RL = 10 kΩ to GND –14.85 V Output Current IOUT ±15 ±25 mA POWER SUPPLY Power Supply Rejection Ratio PSRR VS = ± 1.5 V to ± 15 V 90 110 dB VS = ± 1.5 V to ± 15 V, –40°C ≤ TA ≤ +125°C85 dB Supply Current ISY VO = 0 V, RL = ∞, VS = ± 18 V, –40 °C ≤ T A ≤ +125°C 175 µA Supply Voltage Range VS +3 ( ±1.5) +36 ( ±18) V DYNAMIC PERFORMANCE Slew Rate SR RL = 10 kΩ 0.03 V/ µs Gain Bandwidth Product GBP 85 kHz Phase Margin θ O 83 Degrees NOISE PERFORMANCE Voltage Noise en p-p 0.1 Hz to 10 Hz 1.25 µV p-p Voltage Noise Density en f =1 kHz 45 nV/ √Hz Current Noise Density in f = 1 kHz <0.1 pA/ √Hz Specifications subject to change without notice. WAFER TEST LIMITS Parameter Symbol Conditions Limit Units Offset Voltage Vos 300 µV max Input Bias Current IB 20 nA max Input Offset Current IOS ±2 nA max Input Voltage Range 1 VCM 0 to +4 V min Common-Mode Rejection Ratio CMRR 0 V ≤ V CM ≤ 4 V 90 dB min Power Supply Rejection Ratio PSRR ±1.5 V ≤ V S ≤ ± 15 V 90 µV/V Large Signal Voltage Gain AVO RL = 10 k Ω 1000 V/mV min Output Voltage Swing High VOH RL = 10 k Ω 4.9 V min Supply Current Per Amplifier ISY VOUT = 2.5 V, RL = ∞ 150 µA max NOTES Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. 1Guaranteed by CMRR test. ORDERING GUIDE OP295/OP495 REV. B –3– (@ VS = ±15.0 V, T A = +25 C unless otherwise noted) Temperature Package Package Model Range Description Option OP295GP –40 °C to +125°C 8-Pin Plastic DIP N-8 OP295GS –40 °C to +125°C 8-Pin SOIC SO-8 OP295GBC +25 °C DICE Temperature Package Package Model Range Description Option OP495GP –40 °C to +125°C 14-Pin Plastic DIP N-14 OP495GS –40 °C to +125°C 16-Pin SOL R-16 OP495GBC +25 °C DICE (@ VS = +5.0 V, VCM = 2.5 V, TA = +25 C unless otherwise noted) |
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