ADAU1977WBCPZ-R7 datasheet(1/64 Pages) AD

Teilenummer	ADAU1977WBCPZ-R7

Bauteilbeschribung	Quad ADC with Diagnostics

PDF	64 Pages

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Hersteller	AD [Analog Devices]

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Quad ADC with Diagnostics

Data Sheet

ADAU1977

Rev. A

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FEATURES

Programmable microphone bias (5 V to 9 V) with diagnostics

Four 10 V rms capable direct-coupled differential inputs

On-chip PLL for master clock

Low EMI design

106 dB ADC dynamic range

−95 dB THD + N

Selectable digital high-pass filter

24-bit ADC with 8 kHz to 192 kHz sample rates

Digital volume control with autoramp function

I2C/SPI control

Software-controllable clickless mute

Software power-down

Right justified, left justified, I2S justified, and TDM modes

Master and slave operation modes

40-lead LFCSP package

Qualified for automotive applications

APPLICATIONS

Automotive audio systems

Active noise cancellation system

GENERAL DESCRIPTION

The ADAU1977 incorporates four high performance analog-to-

digital converters (ADCs) with direct-coupled inputs capable of

10 V rms. The ADC uses multibit sigma-delta (Σ-Δ) architecture

with continuous time front end for low EMI. The ADCs can be

connected to the electret microphone (ECM) directly and pro-

vide the bias for powering the microphone. Built-in diagnostic

circuitry detects faults on input lines and includes comprehensive

diagnostics for faults on microphone inputs. The faults reported

are short to battery, short to microphone bias, short to ground,

short between positive and negative input pins, and open input

terminals. In addition, each diagnostic fault is available as an

IRQ flag for ease in system design. An I2C/SPI control port is

also included. The ADAU1977 uses only a single 3.3 V supply.

The part internally generates the microphone bias voltage. The

microphone bias is programmable in a few steps from 5 V to 9 V.

The low power architecture reduces the power consumption.

An on-chip PLL can derive the master clock from an external

clock input or frame clock (sample rate clock). When fed with

a frame clock, the PLL eliminates the need for a separate high

frequency master clock in the system. The ADAU1977 is

available in a 40-lead LFCSP package.

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

MICBIAS

MB_GND

DIAGNOSTICS

AIN1P

SCL/CCLK

SDA/COUT

ADDR1/CIN

ADDR0/CLATCH

FAULT

PD/RST

AIN1N

AIN2P

AIN2N

AIN3P

AIN3N

AIN4P

AIN4N

VBAT

AVDDx

AVDD2

AGNDx

BG

REF

I2C/SPI

CONTROL

5V TO 9V

PROG

BIAS

PLL

AGND2

PGND

DVDD

IOVDD

LRCLK

BCLK

SDATAOUT1

SDATAOUT2

BOOST

CONVERTER

IOUT 50mA

3.3V TO 1.8V

REGULATOR

ADAU1977

ADC

AGND1

AGND2

AGND3

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