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74F794 Datenblatt(PDF) 2 Page - Fairchild Semiconductor |
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74F794 Datenblatt(HTML) 2 Page - Fairchild Semiconductor |
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2 / 6 page ![]() www.fairchildsemi.com 2 Input Loading/Fan-Out Truth Table Note 1: In this case the output of the register is clocked to the inputs and the overall Q output is unchanged at Qn. Logic Diagram Pin Names Description HIGH/LOW (U.L.) Current OE Output Enable Input 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Inputs 1.0/1.0 20 µA/−0.6 mA D0–D7 D Bus Inputs/ 3.5/1.083 70 µA/−650 µA 3-STATE Outputs 750/106.6 −15 mA/64 mA Q0–Q7 Q Bus Outputs 750/106.6 −15 mA/64 mA Inputs Outputs CP OE QD L or H or ↓ LQn Output, Q L or H or ↓ HQn Input ↑ LQn Output, Q (Note 1) ↑ H D Input |
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