EP4CE115F23I7N datasheet(40/42 Pages) ALTERA

40 / 42 page

1–40

Chapter 1: Cyclone IV Device Datasheet

Glossary

Cyclone IV Device Handbook,

May 2013

Altera Corporation

Volume 3

High-speed receiver and transmitter input and output clock period.

Channel-to-

channel-skew

(TCCS)

High-speed I/O block: The timing difference between the fastest and slowest output edges,

including tCO variation and clock skew. The clock is included in the TCCS measurement.

tcin

Delay from the clock pad to the I/O input register.

tCO

Delay from the clock pad to the I/O output.

tcout

Delay from the clock pad to the I/O output register.

tDUTY

High-speed I/O block: Duty cycle on high-speed transmitter output clock.

tFALL

Signal high-to-low transition time (80–20%).

Input register hold time.

Timing Unit

Interval (TUI)

High-speed I/O block: The timing budget allowed for skew, propagation delays, and data

sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).

tINJITTER

Period jitter on the PLL clock input.

tOUTJITTER_DEDCLK

Period jitter on the dedicated clock output driven by a PLL.

tOUTJITTER_IO

Period jitter on the general purpose I/O driven by a PLL.

tpllcin

Delay from the PLL inclk pad to the I/O input register.

tpllcout

Delay from the PLL inclk pad to the I/O output register.

Transmitter

Output

Waveform

Transmitter output waveforms for the LVDS, mini-LVDS, PPDS and RSDS Differential I/O

Standards:

tRISE

Signal low-to-high transition time (20–80%).

tSU

Input register setup time.

——

Table 1–46. Glossary (Part 4 of 5)

Letter

Term

Definitions

Single-Ended Waveform

Differential Waveform (Mathematical Function of Positive & Negative Channel)

Positive Channel (p) = V

Negative Channel (n) = V

Ground

VOD

0 V

Vos

- n

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