VMusic2 Vinculum VNC1L Module

Datasheet Version 0.98

© Future Technology Devices International Ltd. 2007

Page 

checked to see i� the data read was accepted. �� �0� level on ��I Data �ut means that the data write was accepted. ��

�1� indicates that the internal �u��er is �ull�� and the write should �e repeated. �emem�er that C� must �e held low �or at

least one clock period �e�ore �eing taken high again to continue with the ne�t read or write cycle.

Figure 4 � ��I �lave Data Timing Diagrams

T1

T2

T3

T4

T5

T6

T7

SPICLK

SPICS /

SPI DATA IN

SPI DATA OUT

Ta�le 4 � ��I �lave Data Timing

Time

Description

Min

Typical Max

Unit

T1

��ICLK �eriod

8��

�

�

ns

T2

��ICLK High

20

�

�

ns

T��

��ICLK Low

20

�

�

ns

T4

Input �etup Time

10

�

�

ns

T�

Input Hold Time

10

�

�

ns

T6

�utput Hold Time

2

�

�

ns

T7

�utput Valid Time

�

�

20

ns

Ta�le � � �tatus �egister (��DD = �1�)

Bit

Description

0

RXF#

1

�X�#

2

�

��

�

4

RXFIRQ��

�

�X�IRQ��

6

�

7

�