LCMXO2-640ZE-3TG100C datasheet(2/106 Pages) LATTICE

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DS1035 Introduction_01.6

January 2013

Data Sheet DS1035

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Features

 Flexible Logic Architecture

• Six devices with 256 to 6864 LUT4s and



19 to 335 I/Os

 Ultra Low Power Devices

• Advanced 65 nm low power process

• As low as 19 µW standby power

• Programmable low swing differential I/Os

• Stand-by mode and other power saving options

 Embedded and Distributed Memory

• Up to 240 Kbits sysMEM™ Embedded Block

RAM

• Up to 54 Kbits Distributed RAM

• Dedicated FIFO control logic

 On-Chip User Flash Memory

• Up to 256 Kbits of User Flash Memory

• 100,000 write cycles

• Accessible through WISHBONE, SPI, I

2C and

JTAG interfaces

• Can be used as soft processor PROM or as

Flash memory

 Pre-Engineered Source Synchronous I/O

• DDR registers in I/O cells

• Dedicated gearing logic

• 7:1 Gearing for Display I/Os

• Generic DDR, DDRX2, DDRX4

• Dedicated DDR/DDR2/LPDDR memory with

DQS support

 High Performance, Flexible I/O Buffer

• Programmable sysIO™ buffer supports wide

range of interfaces:

– LVCMOS 3.3/2.5/1.8/1.5/1.2

– LVTTL

–PCI

– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL

– SSTL 25/18

– HSTL 18

– Schmitt trigger inputs, up to 0.5V hysteresis

• I/Os support hot socketing

• On-chip differential termination

• Programmable pull-up or pull-down mode

 Flexible On-Chip Clocking

• Eight primary clocks

• Up to two edge clocks for high-speed I/O



interfaces (top and bottom sides only)

• Up to two analog PLLs per device with



fractional-n frequency synthesis

– Wide input frequency range (10 MHz to



400 MHz)

 Non-volatile, Infinitely Reconfigurable

• Instant-on – powers up in microseconds

• Single-chip, secure solution

• Programmable through JTAG, SPI or I

• Supports background programming of non-vola-

tile memory

• Optional dual boot with external SPI memory

 TransFR™ Reconfiguration

• In-field logic update while system operates

 Enhanced System Level Support

• On-chip hardened functions: SPI, I

2C, timer/

counter

• On-chip oscillator with 5.5% accuracy

• Unique TraceID for system tracking

• One Time Programmable (OTP) mode

• Single power supply with extended operating

range

• IEEE Standard 1149.1 boundary scan

• IEEE 1532 compliant in-system programming

 Broad Range of Package Options

• TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA,

fpBGA, QFN package options

• Small footprint package options

– As small as 2.5x2.5mm

• Density migration supported

• Advanced halogen-free packaging

MachXO2 Family Data Sheet

Introduction

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