PIC16F882_12 datasheet(98/338 Pages) MICROCHIP

98 / 338 page

PIC16F882/883/884/886/887

DS41291G-page 98

 2006-2012 Microchip Technology Inc.

SRCON: SR LATCH CONTROL REGISTER

R/W-0

R/S-0

U-0

R/W-0

SR1(2)

SR0(2)

C1SEN

C2REN

PULSS

PULSR

—

FVREN

bit 7

bit 0

Legend:

S = Bit is set only -

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

SR1: SR Latch Configuration bit(2)

1 =

C2OUT pin is the latch Q output

0 =

C2OUT pin is the C2 comparator output

bit 6

SR0: SR Latch Configuration bits(2)

1 =

C1OUT pin is the latch Q output

0 =

C1OUT pin is the C1 Comparator output

bit 5

C1SEN: C1 Set Enable bit

1 = C1 comparator output sets SR latch

0 = C1 comparator output has no effect on SR latch

bit 4

C2REN: C2 Reset Enable bit

1 = C2 comparator output resets SR latch

0 = C2 comparator output has no effect on SR latch

bit 3

PULSS: Pulse the SET Input of the SR Latch bit

1 = Triggers pulse generator to set SR latch. Bit is immediately reset by hardware.

0 = Does not trigger pulse generator

bit 2

PULSR: Pulse the Reset Input of the SR Latch bit

1 = Triggers pulse generator to reset SR latch. Bit is immediately reset by hardware.

0 = Does not trigger pulse generator

bit 1

Unimplemented: Read as ‘0’

bit 0

FVREN: Fixed Voltage Reference Enable bit

1 = 0.6V Reference FROM INTOSC LDO is enabled

0 = 0.6V Reference FROM INTOSC LDO is disabled

Note 1:

The CxOUT bit in the CMxCON0 register will always reflect the actual comparator output (not the level on

the pin), regardless of the SR latch operation.

To enable an SR Latch output to the pin, the appropriate CxOE and TRIS bits must be properly

configured.

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