AD5544ACPZ-1-R2 datasheet(18/24 Pages) AD

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AD5544/AD5554

Data Sheet

Rev. G | Page 18 of 24

LAYOUT AND POWER SUPPLY BYPASSING

It is good practice to employ a compact, minimum lead length

layout design. The leads to the input should be as direct as possible

with a minimum conductor length. Ground paths should have

low resistance and low inductance.

Similarly, it is good practice to bypass the power supplies with

quality capacitors for optimum stability. Supply leads to the device

should be bypassed with 0.01 μF to 0.1 μF disc or chip ceramic

capacitors. Low ESR 1 μF to 10 μF tantalum or electrolytic capaci-

tors should also be applied at VDD to minimize any transient

disturbance and filter any low frequency ripple (see Figure 26).

Users should not apply switching regulators for VDD due to the

power supply rejection ratio (PSRR) degradation over frequency.

AGNDX

VSS

DGND

AD5544/AD5554

VDD

10µF

0.1µF

10µF

0.1µF

VSS

VDD

Figure 26. Power Supply Bypassing and Grounding Connection

GROUNDING

The DGND and AGNDx pins of the AD5544/AD5554 serve as

digital and analog ground references. To minimize the digital

ground bounce, the DGND terminal should be joined remotely

at a single point to the analog ground plane (see Figure 26).

AD5544ACPZ-1-R2 Datenblatt(PDF) 18 Page - Analog Devices