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AT24C128CSSHMB Datenblatt(PDF) 8 Page - ATMEL Corporation |
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AT24C128CSSHMB Datenblatt(HTML) 8 Page - ATMEL Corporation |
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8 / 22 page ![]() 8 Atmel AT24C128C [DATASHEET] 8734B–SEEPR–9/2012 Figure 6-5. Write Cycle Timing Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. Figure 6-6. Output Acknowledge SCL SDA t WR (1) Stop Condition Start Condition WORDN ACK 8th Bit SCL Data In Data Out Start Acknowledge 9 8 1 |
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