HEF4014BT datasheet(4/14 Pages) NXP

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HEF4014B

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Product data sheet

Rev. 8 — 21 November 2011

4 of 14

NXP Semiconductors

HEF4014B

8-bit static shift register

Functional description

[1]

H = HIGH voltage level; L = LOW voltage level; X = don’t care; nD = HIGH or LOW;

 = LOW-to-HIGH clock transition;  = HIGH-to-LOW clock transition;

Limiting values

[1]

For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.

[2]

For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.

Table 3.

Function table[1]

Number of clock

transitions

Inputs

Outputs

Serial operation



XXX



XXX



XXX





no change

Parallel operation





no change

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

VDD

supply voltage

0.5

+18

IIK

input clamping current

VI < 0.5 V or VI >VDD + 0.5 V

10

input voltage

0.5

VDD + 0.5

IOK

output clamping current

VO < 0.5 V or VO >VDD + 0.5 V

10

II/O

input/output current

10

IDD

supply current

Tstg

storage temperature

65

+150

C

Tamb

ambient temperature

40

+85

C

Ptot

total power dissipation

Tamb = 40 C to +85 C

DIP16 package

[1] -

750

SO16 package

[2] -

500

power dissipation

per output

100

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