HMT312S6DFR6A datasheet(5/48 Pages) HYNIX

Teilenummer	HMT312S6DFR6A

Bauteilbeschribung	DDR3L SDRAM Unbuffered SODIMMs Based on 2Gb D-die

PDF	48 Pages

Scroll/Zoom	100%

Hersteller	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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5 / 48 page

Rev. 1.1 / Sep. 2012

Pin Descriptions

Pin Name

Description

Num

ber

Pin Name

Description

Num

ber

CK[1:0]

Clock Input, positive line

DQ[63:0]

Data Input/Output

CK[1:0]

Clock Input, negative line

DM[7:0]

Data Masks

CKE[1:0]

Clock Enables

DQS[7:0]

Data strobes

RAS

Row Address Strobe

DQS[7:0]

Data strobes, negative line

CAS

Column Address Strobe

EVENT

Temperature event pin

Write Enable

TEST

Logic Analyzer specific test pin (No

connect on SODIMM)

S[1:0]

Chip Selects

RESET

Reset Pin

A[9:0],A11,

A[15:13]

Address Inputs

VDD

Core and I/O Power

A10/AP

Address Input/Autoprecharge

VSS

Ground

A12/BC

Address Input/Burst chop

BA[2:0]

SDRAM Bank Addresses

VREFDQ

Input/Output Reference

ODT[1:0]

On Die Termination Inputs

VREFCA

SCL

Serial Presence Detect (SPD)

Clock Input

VTT

Termination Voltage

SDA

SPD Data Input/Output

VDDSPD

SPD Power

SA[1:0]

SPD Address Inputs

Reserved for future use

Total: 204

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