HDLA-3416 datasheet(7/12 Pages) AVAGO

7 / 12 page

Display Internal Block Diagram

Figure 1 shows the HDLX-3416 display internal block

diagram. The CMOS IC consists of a 4 x 7 Character RAM, a

2 x 4 Attribute RAM, a 5 bit Control Register, a 128 character

ASCII decoder and the refresh circuitry necessary to syn-

chronize the decoding and driving of four 5 x 7 dot matrix

displays.

Four 7 bit ASCII words are stored in the Character RAM.

The IC reads the ASCII data and decodes it via the 128

character ASCII decoder. The ASCII decoder includes the

64 character set of the HPDL-2416, 32 lower case ASCII

symbols, and 32 foreign language symbols.

A 5 bit word is stored in the Control Register. Three fields

within the Control Register provide an 8 level brightness

control, master blank, and extended functions disable.

For each display digit location, two bits are stored in the

Attribute RAM. One bit is used to enable a cursor character

at each digit location. A second bit is used to individually

disable the blanking features at each digit location.

The display is blanked and dimmed through an internal

blanking input on the row drivers. Logic within the IC

allows the user to dim the display either through the BL

input or through the brightness control in the control

BL input, the Master Blank in the Control Register, or the

Digit Blank Disable in the Attribute RAM.

Electrical Description

Pin Function

Description

Chip Enable (CE1 and

CE1 and CE2 must be a logic 0 to write to the display.

CE2, Pins 3 and 4)

Clear (CLR, Pin 5)

When CLR is a logic 0 the ASCII RAM is reset to

20hex (space) and the Control Register/Attribute

RAM is reset to 00hex.

Cursor Enable

CUE determines whether the IC displays the ASCII or

(CUE Pin 11)

the Cursor memory. (1 = Cursor, 0 = ASCII.)

Cursor Select

CU determines whether data is stored in the ASCII

(CU, Pin 10)

RAM or the Attribute RAM/Control Register.

(1 = ASCII, 0 = Attribute RAM/ Control Register.)

Write (WR, Pin 9)

WR must be a logic 0 to store data in the display.

Address Inputs

A0-A1 selects a specific location in the display

(A1 and A0, Pins

memory. Address 00 accesses the far right display

7 and 8)

location. Address 11 accesses the far left location.

Data Inputs (D0-D6,

D0-D6 are used to specify the input data for

Pins 16 – 22)

the display.

VDD (Pin 6)

VDD is the positive power supply input.

GND (Pin 12)

GND is the display ground.

Blanking Input

BL is used to flash the display, blank the

(BL, Pin 14)

display or to dim the display.

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