IO130PDB3V2 datasheet(147/212 Pages) MICROSEMI

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Military ProASIC3/EL Low Power Flash FPGAs

Revision 3

2-133

Table 2-204 • RAM4K9

Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.425 V for A3P250 and A3P1000

Parameter

Description

–1

Std. Units

tAS

Address setup time

0.30 0.35

tAH

Address hold time

0.00 0.00

tENS

REN_B, WEN_B setup time

0.17 0.20

tENH

REN_B, WEN_B hold time

0.12 0.14

tBKS

BLK_B setup time

0.28 0.33

tBKH

BLK_B hold time

0.02 0.03

tDS

Input data (DI) setup time

0.22 0.26

tDH

Input data (DI) hold time

0.00 0.00

tCKQ1

Clock High to new data valid on DO (output retained, WMODE = 0)

2.84 2.53

Clock High to new data valid on DO (flow-through, WMODE = 1)

2.15 3.33

tCKQ2

Clock High to new data valid on DO (pipelined)

1.08 1.27

tC2CWWL

Address collision clk-to-clk delay for reliable write after write on same address –

applicable to closing edge

0.28 0.33

tC2CWWH

Address collision clk-to-clk delay for reliable write after write on same address –

applicable to rising edge

0.26 0.30

tC2CRWH

Address collision clk-to-clk delay for reliable read access after write on same

address – applicable to opening edge

0.38 0.45

tC2CWRH

Address collision clk-to-clk delay for reliable write access after read on same

address – applicable to opening edge

0.42 0.49

tRSTBQ

RESET_B Low to data out Low on DO (flow-through)

1.11 1.31

RESET_B Low to data out Low on DO (pipelined)

1.11 1.31

tREMRSTB

RESET_B removal

0.34 0.40

tRECRSTB

RESET_B recovery

1.81 2.12

tMPWRSTB RESET_B minimum pulse width

0.26 0.30

tCYC

Clock cycle time

3.89 4.57

FMAX

Maximum frequency

257 219 MHz

Note:

For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating values.

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