AD6655ABCPZ-801 datasheet(21/88 Pages) AD

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AD6655

Rev. A | Page 21 of

PIN 1

INDICATOR

DRVDD

D1–

D1+

D2–

D2+

D3–

D3+

D4–

D4+

DCO–

DCO+

D5–

D5+

D6–

D6+

D7–

SCLK/DFS

SDIO/DCS

AVDD

VIN+B

VIN–B

RBIAS

CML

SENSE

VREF

VIN–A

VIN+A

AVDD

SMI SDFS

SMI SCLK/PDWN

SMI SDO/OEB

AD6655

PARALLEL LVDS

TOP VIEW

(Not to Scale)

EXPOSED PADDLE, PIN 0

(BOTTOM OF PACKAGE)

NOTES

1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE

ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO

GROUND FOR PROPER OPERATION.

Figure 10. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)

Table 13. Pin Function Descriptions (Interleaved Parallel LVDS Mode)

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

20, 64

DRGND

Ground

Digital Output Ground.

1, 21

DRVDD

Supply

Digital Output Driver Supply (1.8 V to 3.3 V).

24, 57

DVDD

Supply

Digital Power Supply (1.8 V Nominal.)

36, 45, 46

AVDD

Supply

Analog Power Supply (1.8 V Nominal.)

AGND,

Exposed Pad

Ground

Analog Ground. The exposed thermal pad on the bottom of the package provides the analog

ground for the part. This exposed pad must be connected to ground for proper operation.

ADC Analog

VIN+A

Input

Differential Analog Input Pin (+) for Channel A.

VIN−A

Input

Differential Analog Input Pin (−) for Channel A.

VIN+B

Input

Differential Analog Input Pin (+) for Channel B.

VIN−B

Input

Differential Analog Input Pin (−) for Channel B.

VREF

Input/Output

Voltage Reference Input/Output.

SENSE

Input

Voltage Reference Mode Select. See Table 15 for details.

RBIAS

Input/Output

External Reference Bias Resistor.

CML

Output

Common-Mode Level Bias Output for Analog Inputs.

CLK+

Input

ADC Clock Input—True.

CLK−

Input

ADC Clock Input—Complement.

ADC Fast Detect Outputs

FD0+

Output

Channel A/Channel B LVDS Fast Detect Indicator 0—True. See Table 21 for details.

FD0-

Output

Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 21 for details.

FD1+

Output

Channel A/Channel B LVDS Fast Detect Indicator 1—True. See Table 21 for details.

FD1−

Output

Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 21 for details.

FD2+

Output

Channel A/Channel B LVDS Fast Detect Indicator 2—True See Table 21 for details.

FD2−

Output

Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 21 for details.

FD3+

Output

Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 21 for details.

FD3−

Output

Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 21 for details.

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