ADuC7023BCPZ62I-R7 datasheet(47/96 Pages) AD

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Data Sheet

ADuC7023

| Page 47 of 96

Comparator Interface

The comparator interface consists of a 16-bit MMR, CMPCON, which is described in Table 46.

CMPCON Register

Name:

CMPCON

Address:

0xFFFF0444

Default value:

0x0000

Access:

Read/write

Table 46. CMPCON MMR Bit Descriptions

Bit

Value

Name

Description

15 to 11

Reserved.

CMPEN

Comparator enable bit.

This bit is set by the user to enable the comparator.

This bit is cleared by the user to disable the comparator.

9 to 8

CMPIN

Comparator negative input select bits.

AVDD/2.

ADC3 input.

DAC0 output.

Reserved.

7 to 6

CMPOC

Comparator output configuration bits.

Reserved.

Output on COMPOUT.

IRQ.

CMPOL

Comparator output logic state bit. When low, the comparator output is high if the positive input (CMP0)

is above the negative input (CMP1). When high, the comparator output is high if the positive input is

below the negative input.

4 to 3

CMPRES

Response time.

5 µs response time typical for large signals (2.5 V differential).

17 µs response time typical for small signals (0.65 mV differential).

3 µs typical.

01/10

Reserved.

CMPHYST

Comparator hysteresis bit.

This bit is set by the user to have a hysteresis of about 7.5 mV.

This bit is cleared by the user to have no hysteresis.

CMPORI

Comparator output rising edge interrupt.

This bit is set automatically when a rising edge occurs on the monitored voltage (CMP0).

This bit is cleared by the user by writing a 1 to this bit.

CMPOFI

Comparator output rallying edge interrupt.

This bit is set automatically when a falling edge occurs on the monitored voltage (CMP0).

This bit is cleared by user.

Rev. E

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