LP3906

www.ti.com

SNVS456M – AUGUST 2006 – REVISED MAY 2013

BUCK CONVERTERS SW1, SW2

operation,

−40°C to +125°C.

(1) (2) (3) (4) (5)

Parameter

Test Conditions

Min

Typ

Max

Units

Output Voltage Accuracy

−3

+3

%

Line Regulation

0.089

%/V

Load Regulation

0.0013

%/mA

Eff

Efficiency

Load Current = 250 mA

96

%

Shutdown Supply Current

EN is de-asserted

0.01

µA

Sync Mode Clock Frequency

Synchronized from 13 MHz system

2.0

MHz

clock

Internal Oscillator Frequency

2.0

MHz

Peak Switching Current Limit

2.0

A

(5)

Quiescent Current “On”

No load PFM Mode

33

µA

Pin-Pin Resistance PFET

200

m

Ω

Pin-Pin Resistance NFET

180

m

Ω

Turn On Time

Start up from shut-down

500

µs

Input Capacitor

Capacitance for stability

10

µF

Output Capacitor

Capacitance for stability

10

µF

(1)

All voltages are with respect to the potential at the GND pin.

(2)

Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not specifications, but do represent the most

likely norm.

(3)

(4)

The device maintains a stable, regulated output voltage without a load.

(5)

The Iq can be defined as the standing current of the LP3906 when the I2C bus is active and all other power blocks have been disabled

via the I2C bus, or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two

values can be used by the system designer when the LP3906 is powered using a battery. If the user plans to use the HW enable pins to

disable each block of the IC please contact the factory applications for IQ details.

I/O ELECTRICAL CHARACTERISTICS

(1)

Limit

Parameter

Test Conditions

Units

Min

Max

Input Low Level

0.4

V

Input High Level

1.2

V

(1)

This specification is ensured by design.

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