Low-Jitter, Low-Noise LVDS

Repeater in an SC70 Package

8

_______________________________________________________________________________________

Test Circuit and Timing Diagrams (continued)

Figure 4. Transition Time and Propagation Delay Timing Diagram

IN-

IN+

OUT-

OUT+

O (DIFFERENTIAL)

O (DIFFERENTIAL)

O (DIFFERENTIAL)

80%

80%

20%

20%

O (DIFFERENTIAL)

O (DIFFERENTIAL)

O (DIFFERENTIAL)

VID

1/4

MAX9121

REPEATERS REDUCE ASIC OR FPGA STUB LENGTH ON A MULTIDROP BUS.

1/4

MAX9129

1/4

MAX9121

STUB

WITHOUT

REPEATER

STUB WITH

REPEATER

100

Ω

100

Ω

MAX9155

MAX9155

Typical Operating Circuit