AD9433

Rev. A | Page 7 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

52 51 50 49 48 47 46 45 44 43 42 41 40

38

GND

37

36

33

GND

34

GND

35

GND

39

GND

32

31

DGND

30

D0 (LSB)

28

D2

27

D3

29

D1

2

3

GND

4

GND

7

ENCODE

6

5

1

GND

8

ENCODE

9

GND

10

12

DGND

13

11

GND

14 15 16 17 18 19 20 21 22 23 24 25 26

PIN 1

AD9433

TOP VIEW

(Not to Scale)

NOTES

1. THE EXPOSED PADDLE ON THE UNDERSIDE OF THE PACKAGE MUST

BE SOLDERED TO THE GROUND PLANE. SOLDERING THE EXPOSED

PADDLE TO THE PCB INCREASES THE RELIABILITY OF THE SOLDER

JOINTS, MAXIMIZING THE THERMAL CAPABILITY OF THE PACKAGE.

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 3, 4, 9, 11, 33,

34, 35, 38, 39, 40,

43, 48, 51

GND

Analog Ground.

2, 5, 6, 10, 36, 37,

44, 47, 52

Analog Supply (5 V).

7

ENCODE

Encode Clock for ADC, Complementary.

8

ENCODE

Encode Clock for ADC, True. ADC samples on rising edge of ENCODE.

12, 21, 24, 31

DGND

Digital Output Ground.

13, 22, 23, 32

Digital Output Power Supply (3 V).

14

OR

Out-of-Range Output.

15 to 20, 25 to 30

D11 to D6, D5 to D0

Digital Output.

41

DFS

Data Format Select. Logic low = twos complement, logic high = offset binary; floats low.

42

SFDR MODE

CMOS Control Pin. This pin enables SFDR mode, a proprietary circuit that can improve the SFDR

performance of the AD9433. SFDR mode is useful in applications where the dynamic range of

the system is limited by discrete spurious frequency content caused by nonlinearities in the

ADC transfer function. Set this pin to 0 for normal operation; floats low.

45

VREFIN

Reference Input for ADC (2.5 V Typical). Bypass with 0.1 μF capacitor to ground.

46

VREFOUT

Internal Reference Output (2.5 V Typical).

49

AIN

Analog Input, True.

50

AIN

Analog Input, Complementary.

Exposed Pad (EP)

The exposed paddle on the underside of the package must be soldered to the ground plane.

Soldering the exposed paddle to the PCB increases the reliability of the solder joints, maximiz-

ing the thermal capability of the package.