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ADM1026JSTZ-R7 Datenblatt(PDF) 46 Page - ON Semiconductor

Teilenummer ADM1026JSTZ-R7
Bauteilbeschribung  Complete Thermal System Management Controller
PDF  55 Pages
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Hersteller  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
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ADM1026JSTZ-R7 Datenblatt(HTML) 46 Page - ON Semiconductor

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Table 50. REGISTER 24H, STATUS REGISTER 5 (POWER-ON DEFAULT, 00H)
Bit
Name
R/W
(Note 1)
Description
0
GPIO0 Status = 0
R
R/W
When GPIO0 is configured as an input, this bit is set when GPIO0 is asserted.
(Asserted may be active high or active low depending on setting of Bit 1 in GPIO
Configuration Register 1.)
When GPIO0 is configured as an output, setting this bit asserts GPIO0. (Asserted
may be active high or active low depending on setting of Bit 1 in GPIO Configuration
Register 1.)
1
GPIO1 Status = 0
R
R/W
When GPIO1 is configured as an input, this bit is set when GPIO1 is asserted.
(Asserted may be active high or active low depending on setting of Bit 3 in GPIO
Configuration Register 1.)
When GPIO1 is configured as an output, setting this bit asserts GPIO1. (Asserted
may be active high or active low depending on setting of Bit 3 in GPIO Configuration
Register 1.)
2
GPIO2 Status = 0
R
R/W
When GPIO2 is configured as an input, this bit is set when GPIO2 is asserted.
(Asserted may be active high or active low depending on setting of Bit 5 in GPIO
Configuration Register 1.)
When GPIO2 is configured as an output, setting this bit asserts GPIO2. (Asserted
may be active high or active low depending on setting of Bit 5 in GPIO Configuration
Register 1.)
3
GPIO3 Status = 0
R
R/W
When GPIO3 is configured as an input, this bit is set when GPIO3 is asserted.
(Asserted may be active high or active low depending on setting of Bit 7 in GPIO
Configuration Register 1.)
When GPIO3 is configured as an output, setting this bit asserts GPIO3. (Asserted
may be active high or active low depending on setting of Bit 7 in GPIO Configuration
Register 1.)
4
GPIO4 Status = 0
R
R/W
When GPIO4 is configured as an input, this bit is set when GPIO4 is asserted.
(Asserted may be active high or active low depending on setting of Bit 1 in GPIO
Configuration Register 2.)
When GPIO4 is configured as an output, setting this bit asserts GPIO4. (Asserted
may be active high or active low depending on setting of Bit 1 in GPIO Configuration
Register 2.)
5
GPIO5 Status = 0
R
R/W
When GPIO5 is configured as an input, this bit is set when GPIO5 is asserted.
(Asserted may be active high or active low depending on setting of Bit 3 in GPIO
Configuration Register 2.)
When GPIO5 is configured as an output, setting this bit asserts GPIO5. (Asserted
may be active high or active low depending on setting of Bit 3 in GPIO Configuration
Register 2.)
6
GPIO6 Status = 0
R
R/W
When GPIO6 is configured as an input, this bit is set when GPIO6 is asserted.
(Asserted may be active high or active low depending on setting of Bit 5 in GPIO
Configuration Register 2.)
When GPIO6 is configured as an output, setting this bit asserts GPIO6. (Asserted
may be active high or active low depending on setting of Bit 5 in GPIO Configuration
Register 2.)
7
GPIO7 Status = 0
R
R/W
When GPIO7 is configured as an input, this bit is set when GPIO7 is asserted.
(Asserted may be active high or active low depending on setting of Bit 7 in GPIO
Configuration Register 2.)
When GPIO7 is configured as an output, setting this bit asserts GPIO7. (Asserted
may be active high or active low depending on setting of Bit 7 in GPIO Configuration
Register 2.)
1. GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise.



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