MCP6S92 datasheet(2/40 Pages) MICROCHIP

2 / 40 page

 2004 Microchip Technology Inc.

DS21908A-page 2

MCP6S91/2/3

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

VDD –VSS ........................................................................7.0V

All inputs and outputs..................... VSS –0.3Vto VDD +0.3V

Difference Input voltage ....................................... |VDD –VSS|

Output Short Circuit Current ..................................continuous

Current at Input Pin

.............................................................±2mA

Current at Output and Supply Pins

................................ ±30 mA

Storage temperature .....................................-65°C to +150°C

Junction temperature .................................................. +150°C

ESD protection on all pins (HBM; MM)

................ ≥ 4 kV; 200V

† Notice: Stresses above those listed under “Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at

those or any other conditions above those indicated in the

operational listings of this specification is not implied.

Exposure to maximum rating conditions for extended periods

may affect device reliability.

PIN FUNCTION TABLE

Name

Function

VOUT

Analog Output

CH0, CH1 Analog Inputs

VREF

External Reference Pin

VSS

Negative Power Supply

SPI Chip Select

SPI Serial Data Input

SPI Serial Data Output

SCK

SPI Clock Input

VDD

Positive Power Supply

DC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,

Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL =10 kΩ to VDD/2, SI and SCK are tied low and CS is tied high.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Amplifier Inputs (CH0, CH1)

Input Offset Voltage

VOS

-4

—

G = +1

Input Offset Voltage Mismatch

∆V

—

µV

Between inputs (CH0, CH1)

Input Offset Voltage Drift

∆V

OS/∆TA

—±1.8

—

µV/°C

TA = -40°C to +125°C

Power Supply Rejection Ratio

PSRR

—

G = +1 (Note 1)

Input Bias Current

—

±1

—

CHx = VDD/2

Input Bias Current at

Temperature

—

CHx = VDD/2, TA = +85°C

—

600

—

CHx = VDD/2, TA = +125°C

Input Impedance

ZIN

—1013||7

—

Ω||pF

Input Voltage Range

VIVR

VSS − 0.3

—

VDD + 0.3

(Note 2)

Reference Input (VREF)

Input Impedance

ZIN_REF

—

(5/G)||6

—

Ω||pF

Voltage Range

VIVR_REF

VSS

—VDD

(Note 2)

Amplifier Gain

Nominal Gains

—

1 to 32

—

V/V

+1, +2, +4, +5, +8, +10, +16 or +32

DC Gain Error

G = +1

-0.2

—

+0.2

VOUT ≈ 0.3V to VDD − 0.3V

≥ +2

-1.0

—

+1.0

VOUT ≈ 0.3V to VDD − 0.3V

DC Gain Drift

G = +1

∆G/∆T

—

±0.0002

—

%/°C

TA = -40°C to +125°C

≥ +2

∆G/∆T

—

±0.0004

—

%/°C

TA = -40°C to +125°C

Note

RLAD (RF+RG in Figure 4-1) connects VREF, VOUT and the inverting input of the internal amplifier. The MCP6S92 has

VREF tied internally to VSS, so VSS is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. It is

recommended that the MCP6S92’s VSS pin be tied directly to ground to avoid noise problems.

The MCP6S92’s VIVR and VIVR_REF are not tested in production; they are set by design and characterization.

IQ includes current in RLAD (typically 60 µA at VOUT = 0.3V). Both IQ and IQ_SHDN exclude digital switching currents.

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