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MP3908 Datenblatt(PDF) 8 Page - Monolithic Power Systems |
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MP3908 Datenblatt(HTML) 8 Page - Monolithic Power Systems |
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8 / 11 page ![]() MP3908 – HIGH EFFICIENCY BOOST CONTROLLER MP3908 Rev.0.9 www.MonolithicPower.com 8 8/29/2008 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2008 MPS. All Rights Reserved. QGS1=1nC, VTH=1.7V, VPLT=3V and QG=5nC @ 10V. The MP3908 has its gate driving resistance of around 20Ω at VDR=10V and VGATE = 5V. Based on the loss calculation above, the conduction loss is around 0.629W. The switching loss is around 0.171W, and the gate drive loss is 0.015W. Selecting the Output Diode The output rectifier diode supplies current to the inductor when the MOSFET is off. To reduce losses due to diode forward voltage and recovery time, use a Schottky diode. The diode should be rated for a reverse voltage greater than the output voltage used. Considering the voltage spike during the commutation period, the voltage rating of the diode should be set as 1.5 times the output voltage. For high output voltages (150V or above), a Schottky diode might not be practical. A high-speed ultra-fast recovery silicon rectifier is recommended. Observation of the boost converter circuit shows that the average current through the diode is the average load current, and the peak current through the diode is the peak current through the inductor. The average current rating must be greater than 1.5 times of the maximum load current, and the peak current rating must be greater than the peak inductor current. For the application in page 1, a Vishay SS16 Schottky diode or equivalent part is chosen. Boost Converter: Compensation Design The output of the transconductance error amplifier (COMP) is used to compensate the regulation control system. The system uses two poles and one zero to stabilize the control loop. The poles are fP1, which is set by the output capacitor (C2) and load resistance and fP2, which starts from origin. The zero (fZ1) is set by the compensation capacitor (C3) and the compensation resistor (R3). These parameters are determined by the equations: LOAD 1 P R C2 1 f × × π = 3 R C3 2 1 f 1 Z × × π × = Where RLOAD is the load resistance. The DC mid-band loop gain is: SENSE 2 OUT ET REF LOAD IN EA VDC R V A 3 R V R V G 5 . 0 A × × × × × × × = where VREF is the voltage reference, 0.8V. AET is the gain of error amplifier translator and GEA is the error amplifier transconductance. The ESR zero in this example locates at very high frequency. Therefore, it is not taken into design consideration. There is also a right-half-plane zero (fRHPZ) that exists in continuous conduction mode (inductor current does not drop to zero on each cycle) step-up converters. The frequency of the right half plane zero is: 2 2 OUT LOAD IN RHPZ V L 2 R V f × × π × × = The right-half-plane zero increases the gain and reduces the phase simultaneously, which results in smaller phase margin and gain margin. The worst case happens at the condition of minimum input voltage and maximum output power. In order to achieve system stability, fz1 is placed close to fP1 to cancel the pole. R3 is adjusted to change the voltage gain. Make sure the bandwidth is about 1/10 of the lower one of the ESR zero and the right-half-plane zero. R3 C3 2 1 R C2 1 LOAD × × π × = × × π ET IN REF EA SENSE c OUT A V V G R f 2 C 2 V 3 R 2 × × × × × × π × × = Based on these equations, R3 and C3 can be solved. For the application in page 1, fp1 = 1.35KHz, ESR zero is much higher than the switching frequency and fRHPZ=45.8KHz. Set fz1 to 3.18KHz and make the crossover frequency 8.5kHz, then R3=5kΩ and C3=10nF. Choose 5kΩ and 10nF. |
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