AX500 datasheet(49/262 Pages) MICROSEMI

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Axcelerator Family FPGAs

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Timing Characteristics

Table 2-25 • 2.5V LVCMOS I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 2.3 V, TJ = 70°C

–2 Speed

–1 Speed

Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

LVCMOS25 I/O Module Timing

tDP

Input Buffer

1.95

2.22

2.61

tPY

Output Buffer

3.29

3.74

4.40

tENZL

Enable to Pad Delay through the Output

Buffer—Z to Low

2.48

2.50

2.51

tENZH

Enable to Pad Delay through the Output

Buffer—Z to High

2.48

2.50

2.51

tENLZ

Enable to Pad Delay through the Output

Buffer—Low to Z

5.74

6.54

7.69

tENHZ

Enable to Pad Delay through the Output

Buffer—High to Z

6.60

7.51

8.83

tIOCLKQ

Sequential Clock-to-Q for the I/O Input

0.67

0.77

0.90

tIOCLKY

Clock-to-output Y for the I/O Output Register

and the I/O Enable Register

0.67

0.77

0.90

tSUD

Data Input Set-Up

0.23

0.27

0.31

tSUE

Enable Input Set-Up

0.26

0.30

0.35

tHD

Data Input Hold

0.00

tHE

Enable Input Hold

0.00

tCPWHL

Clock Pulse Width High to Low

0.39

tCPWLH

Clock Pulse Width Low to High

0.39

tWASYN

Asynchronous Pulse Width

0.37

tREASYN

Asynchronous Recovery Time

0.13

0.15

0.17

tHASYN

Asynchronous Removal Time

0.00

tCLR

Asynchronous Clear-to-Q

0.23

0.27

0.31

tPRESET

Asynchronous Preset-to-Q

0.23

0.27

0.31

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