AM7968 datasheet(16/127 Pages) AMD

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AMD

Am7968/Am7969

of the internal byte clock (CLK) and the rising edge of

strobe does not violate tBB specification shown in the

SWITCHING CHARACTERISTICS Section.

The internal byte clock controls the flow of data from the

input register through the shift register. The falling edge

of the internal byte clock delineates the end of one byte

from the start of the next. Due to various tolerances in

the PLL, the period of the internal byte clock may vary

slightly. This effect may cause a shift in the location of

the byte boundary with respect to the falling edge of the

clock. This variation may move the byte boundary and

therefore creates a window during which the part should

not be strobed. This window called the t6 window, is

shown in the figure below. If the part is strobed during

the t6 window data will not be lost however, a sync may

be added and the transmitter latency will be increased

by one byte time.

CLK

–9/8(t1/n) + 9 ns

20 ns

Strobe Stayout Area

(t6 window)

07370F-9

Nominal Byte

Boundary

Sync Acquisition

In case of errors which cause Am7969 Receivers to lose

byte/symbol sync, and on power-up, internal logic de-

tects this loss-re-acquisition of sync and modifies the

CLK output. CLK output is actually a buffered version of

the signal which controls Data transfers inside the

Am7969 Receiver on byte boundaries. Byte boundaries

move when the Am7969 Receiver loses, and re-

acquires sync. To protect slave systems (which may use

this output as a clock synchronous with the incoming

data) from having clocks which are too narrow, the out-

put logic will stretch an output pulse when the pulse

would have been less than a byte-time long. The data

being processed just prior to this re-acquisition of sync

will be lost. The Sync symbol, and all subsequent data

will be processed correctly.

TAXI User Test Modes

TLS input can be used to force the Am7968 Transmitter

into either of the two Test modes. If

TLS is open or termi-

nated to approximately VCC/2 (Test Mode 2), the internal

VCO is switched out and everything is clocked directly

from the

CLK input. The serial output data rate will be at

the CLK bit rate and not at 10X, 11X, or 12X, as is the

case in normal operation. Test Mode 2 will allow testing

of the logic in the Latches, Encoder, and Shifter without

having to first stabilize the PLL clock multiplier. In Test

Mode 1 (

TLS wired to VCC), the PLL is enabled and the

chip operates normally, except that the output is an NRZ

stream (CLK is an input & ACK function is slightly modi-

fied). This will allow testing of all functions at full rate

without needing to perform match loop tests to accom-

modate the data inversion characteristics of NRZI.

Differential

SERIN+/SERIN– inputs can be used to

force the Am7969 Receiver into its Test mode. This will

allow testing of the logic in the Latches, Decoder, and

Shifter without having to first stabilize the the PLL. If

SERIN– is tied to ground, the internal VCO is switched

out and

X1 becomes the internal bit rate clock. The serial

data rate will be at the CLK bit rate, not at 10X, 11X, or

12X, as is the case in normal operation. In this mode,

SERIN+ becomes a single-ended serial data input with

nominal 100K ECL threshold voltages (Referenced to

+5 volts).

These Test Mode switches make the parts determinate,

synchronous systems, instead of statistical, asynchro-

nous ones. An automatic test system will be able to

clock each part through the functional test patterns at

any rate or sequence that is convenient. After the logic

has been verified, the part can be put back into the nor-

mal mode, and the PLL functions verified knowing that

the rest of the chip is functional.

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