AM79C960KCW datasheet(56/127 Pages) AMD

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P R E L I M I N A R Y

AMD

1-398

Am79C960

the completion of transmission, then the PCnet-ISA

controller will set the CERR bit in CSR0. CERR will be

asserted in 10BASE-T mode after transmit if T-MAU is

in Link Fail state. CERR will never cause INTR to be acti-

vated. It will, however, set the ERR bit in CSR0.

Host related transmit exception conditions include

BUFF and UFLO as described in the Transmit Descrip-

tor section.

Receive Operation

The receive operation and features of the PCnet-ISA

controller are controlled by programmable options.

Receive Function Programming

Automatic pad field stripping is enabled by setting the

ASTRP_RCV bit in CSR4; this can provide flexibility in

the reception of messages using the 802.3 frame

format.

All receive frames can be accepted by setting the PROM

bit in CSR15. When PROM is set, the PCnet-ISA con-

troller will attempt to receive all messages, subject to

minimum frame enforcement. Promiscuous mode over-

rides the effect of the Disable Receive Broadcast bit on

receiving broadcast frames.

The point at which the BMU will start to transfer data

from the receive FIFO to buffer memory is controlled by

the RCVFW bits in CSR80. The default established dur-

ing reset is 10b, which sets the threshold flag at 64 bytes

empty.

Automatic Pad Stripping

During reception of an 802.3 frame the pad field can be

stripped automatically. ASTRP_RCV (bit 10 in CSR4) =

1 enables the automatic pad stripping feature. The pad

field will be stripped before the frame is passed to the

FIFO, thus preserving FIFO space for additional frames.

The FCS field will also be stripped, since it is computed

at the transmitting station based on the data and pad

field characters, and will be invalid for a receive frame

that has had the pad characters stripped.

The number of bytes to be stripped is calculated from

the embedded length field (as defined in the IEEE 802.3

definition) contained in the frame. The length indicates

the actual number of LLC data bytes contained in the

message. Any received frame which contains a length

field less than 46 bytes will have the pad field stripped (if

ASTRP_RCV is set). Receive frames which have a

length field of 46 bytes or greater will be passed to the

host unmodified.

Since any valid Ethernet Type field value will always be

greater than a normal 802.3 Length field (

≥46), the

PCnet-ISA controller will not attempt to strip valid Ether-

net frames.

Note that for some network protocols the value passed

in the Ethernet Type and/or 802.3 Length field is not

compliant with either standard and may cause

problems.

The diagram below shows the byte/bit ordering of the re-

ceived length field for an 802.3 compatible frame format.

16907B-13

Preamble

1010....1010

SYNCH

10101011

Dest

ADDR

Srce

ADDR

Length

LLC

DATA

Pad

FCS

Bits

Bytes

46–1500

Bytes

Most

Significant

Byte

Least

Significant

Byte

Bit

Start of Packet

at Time= 0

Increasing Time

Bit

45–0

Bytes

1–1500

Bytes

802.3 Frame and Length Field Transmission Order

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