AM79C975VCW datasheet(191/304 Pages) AMD

191 / 304 page

Am79C973/Am79C975

191

P R E L I M INARY

BCR44: PCI DATA Register Seven (DATA7) Alias

Note: This register is an alias of the DATA register and

also of the DATA_SCALE field of the PCMCR register.

Since these two are read only, BCR44 provides a

means of programming them through the EEPROM.

The contents of this register are copied into the corre-

sponding fields pointed with the DATA_SEL field set to

seven. Bits 15-0 in this register are programmable

through the EEPROM.

Bit

Name

Description

15-10 RES

Reserved locations. Written as

zeros and read as undefined.

9-8

D7_SCALE

These bits correspond to the

DATA_SCALE field of the PMC-

SR (offset Register 44 of the PCI

configuration space, bits 14-13).

Refer

the

description

DATA_SCALE for the meaning of

this field.

Read

accessible

always.

D7_SCALE is read only. Cleared

by H_RESET and is not affected

by S_RESET or setting the STOP

bit.

7-0

DATA7

These bits correspond to the PCI

DATA register (offset register 47

of the PCI configuration space,

bits 7-0). Refer to the description

of DATA register for the meaning

of this field.

Read accessible always. DATA7

read

only.

Cleared

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

BCR45: OnNow Pattern Matching Register 1

Note: This register is used to control and indirectly ac-

cess the Pattern Match RAM (PMR). When BCR45 is

written and the PMAT_MODE bit (bit 7) is 1, Pattern

Match logic is enabled. No bus accesses into PMR are

possible, and BCR46, BCR47, and all other bits in

BCR45 are ignored. When PMAT_MODE is set, a read

of BCR45, BCR46, or BCR47 returns all undefined bits

except for PMAT_MODE.

When BCR45 is written and the PMAT_MODE bit is 0,

the Pattern Match logic is disabled and accesses to the

PMR are possible. Bits 6-0 of BCR45 specify the ad-

dress of the PMR word to be accessed. Following the

write to BCR45, the PMR word may be read by reading

BCR45, BCR46 and BCR47 in any order. To write to

PMR word, the write to BCR45 must be followed by a

write to BCR46 and a write to BCR47 in that order to

complete the operation. The RAM will not actually be

written until the write to BCR47 is complete. The write

to BCR47 causes all 5 bytes (four bytes of BCR46-47

and the upper byte of the BCR45) to be written to what-

ever PMR word is addressed by bits 6:0 of BCR45.

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-8

PMR_B0

Pattern Match RAM Byte 0. This

byte is written into or read from

Byte 0 of the Pattern Match RAM

Read and write accessible al-

ways. PMR_B0 is undefined after

H_RESET, and is unaffected by

S_RESET and the STOP bit.

PMAT_MODEPattern Match Mode. Writing a 1 to

this bit will enable Pattern Match

Mode and should only be done

after the Pattern Match RAM has

been programmed.

Read and write accessible al-

ways. PMAT_MODE is reset to 0

after H_RESET, and is unaffect-

ed by S_RESET and the STOP

bit.

6-0

PMR_ADDRPattern Match Ram Address. These

bits are the Pattern Match Ram

address to be written to or read

from.

Read and write accessible al-

ways. PMR_ADDR is reset to 0

after H_RESET, and is unaffect-

ed by S_RESET and the STOP

bit.

BCR46: OnNow Pattern Matching Register 2

Note: This register is used to control and indirectly ac-

cess the Pattern Match RAM (PMR). When BCR45 is

written and the PMAT_MODE bit (bit 7) is 1, Pattern

Match logic is enabled. No bus accesses into PMR are

possible, and BCR46, BCR47, and all other bits in

BCR45 are ignored. When PMAT_MODE is set, a read

of BCR45, BCR46, or BCR47 returns all undefined bits

except for PMAT_MODE.

When BCR45 is written and the PMAT_MODE bit is 0,

the Pattern Match logic is disabled and accesses to the

PMR are possible. Bits 6-0 of BCR45 specify the ad-

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