AM79C975VCW datasheet(205/304 Pages) AMD

205 / 304 page

Am79C973/Am79C975

205

P R E L I M INARY

If the Logical Address Filter is loaded with all zeros and

promiscuous mode is disabled, all incoming logical ad-

dresses except broadcast will be rejected. If the

DRCVBC bit (CSR15, bit 14) is set as well, the broad-

cast packets will be rejected. See Figure 51.

PADR

This 48-bit value represents the unique node address

assigned by the ISO 8802-3 (IEEE/ANSI 802.3) and

used for internal address comparison. PADR[0] is com-

pared with the first bit in the destination address of the

incoming frame. It must be 0 since only the destination

address of a unicast frames is compared to PADR. The

six hex-digit nomenclature used by the ISO 8802-3

(I EEE/ AN S I 80 2. 3) map s to t h e Am 79 C 9 73/

Am79C975 PADR register as follows: the first byte is

compared with PADR[7:0], with PADR[0] being the

least significant bit of the byte. The second ISO 8802-3

(IEEE/ANSI 802.3) byte is compared with PADR[15:8],

again from the least significant bit to the most signifi-

cant bit, and so on. The sixth byte is compared with

PADR[47:40], the least significant bit being PADR[40].

Mode

The mode register field of the initialization block is cop-

ied into CSR15 and interpreted according to the de-

scription of CSR15.

Figure 51. Address Match Logic

Receive Descriptors

When SWSTYLE (BCR20, bits 7-0) is set to 0, then the

software structures are defined to be 16 bits wide, and

receive descriptors look like Table 58 (CRDA = Current

Receive Descriptor Address).

When SWSTYLE (BCR 20, bits 7-0) is set to 2, then the

software structures are defined to be 32 bits wide, and

receive descriptors look like Table 59 (CRDA = Current

Receive Descriptor Address).

When SWSTYLE (BCR 20, bits 7-0) is set to 3, then the

software structures are defined to be 32 bits wide, and

receive descriptors look like Table 60 (CRDA = Current

Receive Descriptor Address).

Table 58. Receive Descriptor (SWSTYLE = 0)

CRC

GEN

SEL

MUX

Match = 1 Packet Accepted

Match = 0 Packet Rejected

Match

Logical

Address Filter

(LADRF)

32-Bit Resultant CRC

Received Message

Destination Address

21510B-56

Address

151413121110

7-0

CRDA+00h

RBADR[15:0]

CRDA+02h

OWN

ERR

FRAM

OFLO

CRC

BUFF

STP

ENP

RBADR[23:16]

CRDA+04h

1111

BCNT

CRDA+06h

0000

MCNT

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