A7986ATR datasheet(20/42 Pages) STMICROELECTRONICS

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Application information

A7986A

20/42

DocID022801 Rev 5

Equation 21

As seen in Section 5.3, two different kinds of network can compensate the loop. In the two

following paragraphs, the guidelines to select the Type II and Type III compensation network

are illustrated.

6.4.1

Type III compensation network

The methodology to stabilize the loop consists of placing two zeros to compensate the effect

of the LC double pole, therefore increasing phase margin; then to place one pole in the

origin to minimize the DC error on regulated output voltage; finally, to place other poles far

from the zero dB frequency.

If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a

frequency higher than the desired bandwidth (that is: 2

π∗ESR∗COUT<1/BW), the Type III

compensation network is needed. Multi-layer ceramic capacitors (MLCC) have very low

ESR (<1 m

Ω), with very high frequency zero, so a Type III network is adopted to

compensate the loop.

In Figure 10, the Type III compensation network is shown. This network introduces two

zeros (fZ1, fZ2) and three poles (fP0, fP1, fP2). They are expressed as:

Equation 22

Equation 23

OUT

ESR

()

⋅⋅

⋅

OUT

ESR

⋅⋅

------------------------------------------------------------------------------------------

OUT

--------------

π C

()

⋅⋅

------------------------------------------------

π R

⋅⋅

------------------------------

π R

⋅⋅

------------------------------

π R

⋅

--------------------

⋅⋅

--------------------------------------------

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