STM32F407IG datasheet(24/167 Pages) STMICROELECTRONICS

24 / 167 page

Description

STM32F405xx, STM32F407xx

24/167

Doc ID 022152 Rev 2

VDD minimum value is 1.8 V. VDD/VDDA minimum value of 1.7 V is obtained when the device

operates in the 0 to 70 °C temperature range and PDR is disabled.

There are three low-power modes:

–

MR is used in the nominal regulation mode (Run)

–

LPR is used in the Stop modes

–

Power-down is used in Standby mode: the regulator output is in high impedance:

the kernel circuitry is powered down, inducing zero consumption (but the contents

of the registers and SRAM are lost).

●

Regulator ON/internal reset OFF

The regulator ON with internal reset OFF mode is not available on LQFP64 and

LQFP100 packages.

On LQFP144, and LQFP176 packages, the internal reset is controlled by applying an

inverted reset signal to PDR_ON pin.

On UFBGA176 package, the internal regulator must be activated by connecting

BYPASS_REG to VSS.

On LQFP176 packages, the internal reset must be activated by applying an inverted

reset signal to PDR_ON pin.

The NRST pin should be controlled by an external reset controller to keep the device

under reset when VDD is below 1.8 V (see Figure 7).

Figure 7.

Regulator ON/internal reset OFF

STM32F407IG Datenblatt(PDF) 24 Page - STMicroelectronics