DAC8143FS datasheet(9/12 Pages) AD

9 / 12 page

DAC8143

–9–

REV. C

Table I. Truth Table

DAC8143 Logic Inputs

Input Register/

Digital Output

Control Inputs

DAC Register

Control Inputs

STB4

STB

STB2

STB1

CLR

DAC8143 Operation

Notes

Serial Data Bit Loaded from SRI

into Input Register and Digital Output

2, 3

(SRO Pin) after 12 Clocked Bits.

No Operation (Input Register and SRO)

Reset DAC Register to Zero Code

(Code: 0000 0000 0000)

1, 3

(Asynchronous Operation)

No Operation (DAC Register and SRO)

Load DAC Register with the Contents

of Input Register

NOTES

CLR = 0 asynchronously resets DAC Register to 0000 0000 0000, but has no effect on Input Register.

2Serial data is loaded into Input Register MSB first, on edges shown. g is positive edge, f is negative edge.

30 = Logic LOW, 1 = Logic HIGH, X = Don’t Care.

APPLICATIONS INFORMATION

UNIPOLAR OPERATION (2-QUADRANT)

The circuit shown in Figures 16 and 17 may be used with an ac

or dc reference voltage. The circuit’s output will range between

0 V and +10(4095/4096) V depending upon the digital input

code. The relationship between the digital input and the analog

output is shown in Table II. The VREF voltage range is the maxi-

mum input voltage range of the op amp or

±25 V, whichever is

lowest.

Table II. Unipolar Code Table

Digital Input

Nominal Analog Output

(VOUT as Shown

MSB

LSB

in Figures 16 and 17)

1 1 1 1 1 1 1 1 1 1 1 1

–VREF

4095

4096









1 0 0 0 0 0 0 0 0 0 0 1

–VREF

2049

4096









1 0 0 0 0 0 0 0 0 0 0 0

–VREF

2048

4096







 = –

VREF

0 1 1 1 1 1 1 1 1 1 1 1

–VREF

2047

4096









0 0 0 0 0 0 0 0 0 0 0 1

–VREF

4096









0 0 0 0 0 0 0 0 0 0 0 0

–VREF

4096







 = 0

NOTES

1Nominal full scale for the circuits of Figures 16 and 17 is given by

FS = –VREF

4095

4096









2Nominal LSB magnitude for the circuits of Figures 16 and 17 is given by

LSB = VREF

4096









or VREF(2

–n).

OP-77

+5V

VREF

VDD

RFEEDBACK

IOUT1

IOUT2

AGND

DGND

SRO

(BUFFERED

DIGITAL

DATA OUT)

15pF

+15V

–15V

VOUT

4, 5

8–11

DAC8143

CONTROL

INPUTS

SRI

(SERIAL

DATA IN)

VREF

–10V

CLR

Figure 16. Unipolar Operation with High Accuracy Op

Amp (2-Quadrant)

OP-42

+5V

VREF

VDD

RFEEDBACK

IOUT1

IOUT2

AGND

DGND

SRO

(BUFFERED

DIGITAL

DATA OUT)

15pF

+15V

–15V

VOUT

4, 5

8–11

DAC8143

CONTROL

INPUTS

SRI

(SERIAL

DATA IN)

VREF

–10V

100

CLR

Figure 17. Unipolar Operation with Fast Op Amp and

Gain Error Trimming (2-Quadrant)

DAC8143FS Datenblatt(PDF) 9 Page - Analog Devices

DAC8143FS Datenblatt(HTML) 9 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

Datenblatt Download

Link URL