PIC24F16KA102T-E datasheet(201/278 Pages) MICROCHIP

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DS39927C-page 201

PIC24F16KA102 FAMILY

26.2

Watchdog Timer (WDT)

For the PIC24F16KA102 family of devices, the WDT is

driven by the LPRC oscillator. When the WDT is

enabled, the clock source is also enabled.

The nominal WDT clock source from LPRC is 31 kHz.

This feeds a prescaler that can be configured for either

5-bit (divide-by-32) or 7-bit (divide-by-128) operation.

The prescaler is set by the FWPSA Configuration bit.

With a 31 kHz input, the prescaler yields a nominal

WDT time-out period (TWDT) of 1 ms in 5-bit mode or

4 ms in 7-bit mode.

A variable postscaler divides down the WDT prescaler

output and allows for a wide range of time-out periods.

The postscaler is controlled by the Configuration bits,

WDTPS<3:0> (FWDT<3:0>), which allow the selection

of a total of 16 settings, from 1:1 to 1:32,768. Using the

prescaler and postscaler time-out periods, ranging

from 1 ms to 131 seconds, can be achieved.

The WDT, prescaler and postscaler are reset:

• On any device Reset

• On the completion of a clock switch, whether

invoked by software (i.e., setting the OSWEN bit

after changing the NOSC bits) or by hardware

(i.e., Fail-Safe Clock Monitor)

• When a PWRSAV instruction is executed

(i.e., Sleep or Idle mode is entered)

• When the device exits Sleep or Idle mode to

resume normal operation

•By a CLRWDT instruction During normal execution

If the WDT is enabled, it will continue to run during

Sleep or Idle modes. When the WDT time-out occurs,

the device will wake the device and code execution will

continue from where the PWRSAV instruction was

executed. The corresponding SLEEP or IDLE bits

(RCON<3:2>) will need to be cleared in software after

the device wakes up.

The WDT Flag bit, WDTO (RCON<4>), is not

automatically cleared following a WDT time-out. To

detect subsequent WDT events, the flag must be

cleared in software.

26.2.1

WINDOWED OPERATION

The Watchdog Timer has an optional Fixed Window

mode of operation. In this Windowed mode, CLRWDT

instructions can only reset the WDT during the last

1/4 of the programmed WDT period. A CLRWDT instruc-

tion executed before that window causes a WDT

Reset, similar to a WDT time-out.

Windowed WDT mode is enabled by programming the

Configuration bit, WINDIS (FWDT<6>), to ‘0’.

26.2.2

CONTROL REGISTER

The WDT is enabled or disabled by the FWDTEN

Configuration bit. When the FWDTEN Configuration bit

is set, the WDT is always enabled.

The WDT can be optionally controlled in software when

the FWDTEN Configuration bit has been programmed

to ‘0’. The WDT is enabled in software by setting the

SWDTEN control bit (RCON<5>). The SWDTEN

control bit is cleared on any device Reset. The software

WDT option allows the user to enable the WDT for

critical code segments and disable the WDT during

non-critical segments for maximum power savings.

FIGURE 26-1:

WDT BLOCK DIAGRAM

Note:

The CLRWDT and PWRSAV instructions

clear the prescaler and postscaler counts

when executed.

LPRC Input

WDT Overflow

Wake from Sleep

31 kHz

Prescaler

Postscaler

FWPSA

SWDTEN

FWDTEN

Reset

All Device Resets

Sleep or Idle Mode

LPRC Control

CLRWDT

Instr.

PWRSAV

Instr.

(5-Bit/7-Bit)

1:1 to 1:32.768

WDTPS<3:0>

1 ms/4 ms

Exit Sleep or

Idle Mode

WDT

Counter

Transition to

New Clock Source

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