PIC24F16KA102T-E datasheet(135/278 Pages) MICROCHIP

135 / 278 page

 2008-2011 Microchip Technology Inc.

DS39927C-page 135

PIC24F16KA102 FAMILY

bit 1

SPITBF:

SPI1 Transmit Buffer Full Status bit

= Transmit has not yet started, SPI1TXB is full

= Transmit has started, SPI1TXB is empty

In Standard Buffer mode:

Automatically set in hardware when the CPU writes to the SPITBF location, loading SPITBF.

Automatically cleared in hardware when the SPI1 module transfers data from SPI1TXB to SPIRBF.

In Enhanced Buffer mode:

Automatically set in hardware when CPU writes to the SPI1BUF location, loading the last available buffer location.

Automatically cleared in hardware when a buffer location is available for a CPU write.

bit 0

SPIRBF:

SPI1 Receive Buffer Full Status bit

= Receive is complete; SPI1RXB is full

= Receive is not complete; SPI1RXB is empty

In Standard Buffer mode:

Automatically set in hardware when SPI1 transfers data from SPIRBF to SPIRBF.

Automatically cleared in hardware when the core reads the SPI1BUF location, reading SPIRBF.

In Enhanced Buffer mode:

Automatically set in hardware when SPI1 transfers data from SPI1SR to buffer, filling the last unread buffer location.

Automatically cleared in hardware when a buffer location is available for a transfer from SPI1SR.

SPI1STAT: SPI1 STATUS AND CONTROL REGISTER (CONTINUED)

PIC24F16KA102T-E Datenblatt(PDF) 135 Page - Microchip Technology