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PIC24F16KA102T-E Datenblatt(PDF) 181 Page - Microchip Technology |
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PIC24F16KA102T-E Datenblatt(HTML) 181 Page - Microchip Technology |
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181 / 278 page ![]() 2008-2011 Microchip Technology Inc. DS39927C-page 181 PIC24F16KA102 FAMILY EQUATION 22-1: A/D CONVERSION CLOCK PERIOD(1) FIGURE 22-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled. TAD = TCY • (ADCS + 1) TAD TCY ADCS = – 1 CPIN VA Rs ANx VT = 0.6V VT = 0.6V ILEAKAGE RIC 250 Sampling Switch RSS CHOLD = A/D capacitance VSS VDD = 4.4 pF (Typical) ±500 nA Legend: CPIN VT ILEAKAGE RIC RSS CHOLD = Input Capacitance = Threshold Voltage = Leakage Current at the pin due to = Interconnect Resistance = Sampling Switch Resistance = Sample/Hold Capacitance (from A/D) various junctions Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs 5 k. RSS 5 k (Typical) 6-11 pF (Typical) |
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