TS68302VR1BSLASHT16 datasheet(27/47 Pages) ATMEL

27 / 47 page

TS68302

2117A–HIREL–11/02

Note:

1. Set up time for the asynchronous inputs IPL2-IPL0 and AVEC guarantees their recognition at the next falling edge of the

clock.

2. See Figure 20.

Figure 20. Interrupts Timing Diagram

Note:

1. FRZ should be negated during total system reset.

2. See Figure 21.

Figure 21. Timers Timing Diagram

Table 16. AC Electrical Specifications - Interrupts

(2) f = 16.67 MHz

Num.

Symbol

Parameter

Min

Max

Unit

190

IPW

Interrupt pulse width low IRQ (edge triggered mode)

191

tAEMT

Minimum time between active edges

clk

IRQ

(INPUT)

191

190

Table 17. AC Electrical Specifications - Timers(2) f = 16.67 MHz

Num.

Symbol

Parameter

Min

Max

Unit

200

TPW

Timer input capture pulse width

201

TICLT

TIN clock low pulse width

202

TICHT

TIN clock high pulse width

clk

203

cyc

TIN clock cycle time

clk

204

CHTOV

Clock high to TOUT valid

205

FRZSU

FRZ input setup time (to clock high)

(1)

206

FRZHT

FRZ input hold time (from clock high)

CLKO

204

202

201

203

TIN

(INPUT)

TOUT

(OUTPUT)

206

205

FRZ

(INPUT)

200

TS68302VR1B/T16 Datenblatt(PDF) 27 Page - ATMEL Corporation

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