®

DAC56

5

FIGURE 4. Input Timing Diagram.

INPUT TIMING CONSIDERATIONS

Figures 4 and 5 refer to the input timing required to interface

the inputs of DAC56 to a serial input data stream. Serial data

is accepted in Binary Two’s Complement with the MSB being

loaded first. Data is clocked in on positive going clock (CLK,

pin 5) edges and is latched into the DAC input register on

negative going latch enable (LE, pin 6) edges.

The latch enable input must be high for at least one clock cycle

before going low, and then must be held low for at least one

clock cycle. The last 16 data bits clocked into the serial input

register are those that are transferred to the DAC input register

when latch enable goes low. In other words, when more than

16 clock cycles occur between a latch enable, only the data

present during the last 16 clocks will be transferred to the

DAC input register.

Figure 4 gives the general input format required for the

DAC56. Figure 5 shows the specific relationships between the

various signals and their timing constraints.

FIGURE 5. Input Timing Relationships.

MSB

DATA

> 40ns

> One Clock Cycle

LE

> One Clock Cycle

CLK

> 40ns

> 5ns

> 100ns

LSB

>15ns >15ns

> 40ns

> 15ns

DATA

LE

2

(2)

CLK

(3)

MSB

LSB

MSB

(4)

(1)

NOTES: (1) If clock is stopped between input of 16-bit data words, latch enable (LE) must remain low until after the first clock of the next 16-bit data

word stream. (2) Data format is binary two's complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch

enable (LE) must remain low at least one clock cycle after going negative. (4) Latch enable (LE) must be high for at least one clock cycle before going

negative.

1

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1