CS43L43 datasheet(31/36 Pages) CIRRUS

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CS43L43

DS479PP3

SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK (Inputs: Logic “0” =

GND, Logic “1” = VL.)

Notes: 6. In Internal SCLK Mode, the LRCK duty cycle must be 50%

+/− 1/2 MCLK Period.

Parameters

Symbol

Min

Typ

Max

Units

Internal SCLK Mode

LRCK Duty Cycle

(Note 6)

-50

SCLK Period

tsclkw

SCLK rising to LRCK edge

tsclkr

SDATA valid to SCLK rising setup time

tsdlrs

SCLK rising to SDATA hold time

Single-Speed Mode

tsdh

Double-Speed Mode

tsdh

SCLK

-----------------

tsclkw

------------------

512

()Fs

----------------------10

512

()Fs

----------------------15

384

(

)Fs

----------------------15

Figure 20. Internal Serial

Mode Input Timing

*The SCLK pulses shown are internal to the CS43L43.

SD A T A

*IN T E R N A L

SC L K

LR C K

sc lk w

sd lrs

sdh

sc lk r

SD A TA

LR C K

MC LK

*INT E R NA L S C LK

Figure 21. Internal Serial Clock Generation

* The SCLK pulses shown are internal to the CS43L43.

N equals MCLK divided by SCLK

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