 |
Datenblatt-Suchmaschine für elektronische Bauteile |
|
|
Datenblatt-Suchmaschine für elektronische Bauteile |
|
CS49400 Datenblatt(PDF) 25 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
CS49400 Datenblatt(HTML) 25 Page - Cirrus Logic |
|
|
25 / 100 page  25 1.17 Switching Characteristics — Parallel Data Input (DSPAB) (TA =25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL =20pF) Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can be defined as follows: Internal Clock Mode: DCLK ~ 60MHz before and during boot, i.e. DCLKP ~ 16.6ns DCLK ~ 86 MHz after boot, i.e. DCLKP ~ 11.6ns It should be noted that DCLK for the internal clock mode is application specific. The application code users guide should be checked to confirm DCLK for the particular application. Parameter Symbol Min Max Unit CMPCLK Period Tcmpclk 4*DCLKP + 10 ns FDAT[7:0] setup before CMPCLK high Tcmpsu 10 ns FDAT[7:0] hold after CMPCLK high Tcmphld 10 ns CMPC LK Tcmpsu Tcmpclk FD AT[7:0] Tcmphld Figure 16. Parallel Data Timing |
|
Link URL |
| War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Link zum Datenblatt | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
German ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
