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DS1021 Datenblatt(PDF) 7 Page - Dallas Semiconductor |
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DS1021 Datenblatt(HTML) 7 Page - Dallas Semiconductor |
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7 / 9 page ![]() DS1021 7 of 9 (cont’d) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Parallel Input Change to Delay Invalid tPDX 0ns Enable to Delay Valid tEDV 50 µs Enable to Delay Invalid tEDX 0ns VCC Valid to Device Functional tPU 100 ms VCC Rise Time tVR 20 ms Input Pulse Width tWI 100% of Output Delay ns Input to Output Delay tPLH, tPHL Table 2 ns 2 Input Period Period 2 (tWI)ns CAPACITANCE (TA = 25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance CIN 10 pF TIMING DIAGRAM: SILICON DELAY LINE Figure 5 |
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