DS2433

2 of 19

from the 1-Wire communication line. The memory is organized as sixteen pages of 256 bits each. The

scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to the

scratchpad where it may be read back for verification. A copy scratchpad command will then transfer the

data to memory. This process insures data integrity when modifying the memory. The 64-bit registration

number provides a guaranteed unique identity which allows for absolute traceability and acts as node

address if multiple DS2433 are connected in parallel to form a local network. Data is transferred serially

via the 1-Wire protocol which requires only a single data lead and a ground return. The PR-35 and SOIC

packages provide a compact enclosure that allows standard assembly equipment to handle the device

easily for attachment to printed circuit boards or wiring.

Typical applications include storage of

calibration constants, board identification and product revision status.

OVERVIEW

The block diagram in Figure 1 shows the relationships between the major control and memory sections of

the DS2433.

The DS2433 has three main data components: 1) 64-bit lasered ROM, 2) 256-bit

scratchpad, and 3) 4096-bit EEPROM. The hierarchical structure of the 1-Wire protocol is shown in

Figure 2. The bus master must first provide one of the six ROM Function Commands, 1) Read ROM, 2)

Match ROM, 3) Search ROM, 4) Skip ROM, 5) Overdrive-Skip ROM or 6) Overdrive-Match ROM.

Upon completion of an overdrive ROM command byte executed at standard speed, the device will enter

Overdrive mode where all subsequent communication occurs at a higher speed. The protocol required for

these ROM function commands is described in Figure 9. After a ROM function command is successfully

executed, the memory functions become accessible and the master may provide any one of the four

memory function commands. The protocol for these memory function commands is described in Figure

7. All data is read and written least significant bit first.

PARASITE POWER

The block diagram (Figure 1) shows the parasite-powered circuitry.

This circuitry “steals” power

whenever the I/O input is high. I/O will provide sufficient power as long as the specified timing and

voltage requirements are met.

DS2433 BLOCK DIAGRAM Figure 1